1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2015 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * Fabio Estevam <fabio.estevam@freescale.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __MAX77696_PMIC_H__ 9*4882a593Smuzhiyun #define __MAX77696_PMIC_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define CONFIG_POWER_MAX77696_I2C_ADDR 0x3C 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun enum { 14*4882a593Smuzhiyun L01_CNFG1 = 0x43, 15*4882a593Smuzhiyun L01_CNFG2, 16*4882a593Smuzhiyun L02_CNFG1, 17*4882a593Smuzhiyun L02_CNFG2, 18*4882a593Smuzhiyun L03_CNFG1, 19*4882a593Smuzhiyun L03_CNFG2, 20*4882a593Smuzhiyun L04_CNFG1, 21*4882a593Smuzhiyun L04_CNFG2, 22*4882a593Smuzhiyun L05_CNFG1, 23*4882a593Smuzhiyun L05_CNFG2, 24*4882a593Smuzhiyun L06_CNFG1, 25*4882a593Smuzhiyun L06_CNFG2, 26*4882a593Smuzhiyun L07_CNFG1, 27*4882a593Smuzhiyun L07_CNFG2, 28*4882a593Smuzhiyun L08_CNFG1, 29*4882a593Smuzhiyun L08_CNFG2, 30*4882a593Smuzhiyun L09_CNFG1, 31*4882a593Smuzhiyun L09_CNFG2, 32*4882a593Smuzhiyun L10_CNFG1, 33*4882a593Smuzhiyun L10_CNFG2, 34*4882a593Smuzhiyun LDO_INT1, 35*4882a593Smuzhiyun LDO_INT2, 36*4882a593Smuzhiyun LDO_INT1M, 37*4882a593Smuzhiyun LDO_INT2M, 38*4882a593Smuzhiyun LDO_CNFG3, 39*4882a593Smuzhiyun SW1_CNTRL, 40*4882a593Smuzhiyun SW2_CNTRL, 41*4882a593Smuzhiyun SW3_CNTRL, 42*4882a593Smuzhiyun SW4_CNTRL, 43*4882a593Smuzhiyun EPDCNFG, 44*4882a593Smuzhiyun EPDINTS, 45*4882a593Smuzhiyun EPDINT, 46*4882a593Smuzhiyun EPDINTM, 47*4882a593Smuzhiyun EPDVCOM, 48*4882a593Smuzhiyun EPDVEE, 49*4882a593Smuzhiyun EPDVNEG, 50*4882a593Smuzhiyun EPDVPOS, 51*4882a593Smuzhiyun EPDVDDH, 52*4882a593Smuzhiyun EPDSEQ, 53*4882a593Smuzhiyun EPDOKINTS, 54*4882a593Smuzhiyun CID = 0x9c, 55*4882a593Smuzhiyun PMIC_NUM_OF_REGS, 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun int power_max77696_init(unsigned char bus); 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #endif 61