1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2013 Samsung Electronics 3*4882a593Smuzhiyun * Piotr Wilczek <p.wilczek@samsung.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __MAX77693_MUIC_H_ 9*4882a593Smuzhiyun #define __MAX77693_MUIC_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <power/power_chrg.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * MUIC REGISTER 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define MAX77693_MUIC_PREFIX "max77693-muic:" 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* MAX77693_MUIC_STATUS1 */ 20*4882a593Smuzhiyun #define MAX77693_MUIC_ADC_MASK 0x1F 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* MAX77693_MUIC_STATUS2 */ 23*4882a593Smuzhiyun #define MAX77693_MUIC_CHG_NO 0x00 24*4882a593Smuzhiyun #define MAX77693_MUIC_CHG_USB 0x01 25*4882a593Smuzhiyun #define MAX77693_MUIC_CHG_USB_D 0x02 26*4882a593Smuzhiyun #define MAX77693_MUIC_CHG_TA 0x03 27*4882a593Smuzhiyun #define MAX77693_MUIC_CHG_TA_500 0x04 28*4882a593Smuzhiyun #define MAX77693_MUIC_CHG_TA_1A 0x05 29*4882a593Smuzhiyun #define MAX77693_MUIC_CHG_MASK 0x07 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* MAX77693_MUIC_CONTROL1 */ 32*4882a593Smuzhiyun #define MAX77693_MUIC_CTRL1_DN1DP2 ((0x1 << 3) | 0x1) 33*4882a593Smuzhiyun #define MAX77693_MUIC_CTRL1_UT1UR2 ((0x3 << 3) | 0x3) 34*4882a593Smuzhiyun #define MAX77693_MUIC_CTRL1_ADN1ADP2 ((0x4 << 3) | 0x4) 35*4882a593Smuzhiyun #define MAX77693_MUIC_CTRL1_AUT1AUR2 ((0x5 << 3) | 0x5) 36*4882a593Smuzhiyun #define MAX77693_MUIC_CTRL1_MASK 0xC0 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define MUIC_PATH_USB 0 39*4882a593Smuzhiyun #define MUIC_PATH_UART 1 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define MUIC_PATH_CP 0 42*4882a593Smuzhiyun #define MUIC_PATH_AP 1 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun enum muic_path { 45*4882a593Smuzhiyun MUIC_PATH_USB_CP, 46*4882a593Smuzhiyun MUIC_PATH_USB_AP, 47*4882a593Smuzhiyun MUIC_PATH_UART_CP, 48*4882a593Smuzhiyun MUIC_PATH_UART_AP, 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* MAX 777693 MUIC registers */ 52*4882a593Smuzhiyun enum { 53*4882a593Smuzhiyun MAX77693_MUIC_ID = 0x00, 54*4882a593Smuzhiyun MAX77693_MUIC_INT1 = 0x01, 55*4882a593Smuzhiyun MAX77693_MUIC_INT2 = 0x02, 56*4882a593Smuzhiyun MAX77693_MUIC_INT3 = 0x03, 57*4882a593Smuzhiyun MAX77693_MUIC_STATUS1 = 0x04, 58*4882a593Smuzhiyun MAX77693_MUIC_STATUS2 = 0x05, 59*4882a593Smuzhiyun MAX77693_MUIC_STATUS3 = 0x06, 60*4882a593Smuzhiyun MAX77693_MUIC_INTMASK1 = 0x07, 61*4882a593Smuzhiyun MAX77693_MUIC_INTMASK2 = 0x08, 62*4882a593Smuzhiyun MAX77693_MUIC_INTMASK3 = 0x09, 63*4882a593Smuzhiyun MAX77693_MUIC_CDETCTRL = 0x0A, 64*4882a593Smuzhiyun MAX77693_MUIC_CONTROL1 = 0x0C, 65*4882a593Smuzhiyun MAX77693_MUIC_CONTROL2 = 0x0D, 66*4882a593Smuzhiyun MAX77693_MUIC_CONTROL3 = 0x0E, 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun MUIC_NUM_OF_REGS = 0x0F, 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define MAX77693_MUIC_I2C_ADDR (0x4A >> 1) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun int power_muic_init(unsigned int bus); 74*4882a593Smuzhiyun #endif /* __MAX77693_MUIC_H_ */ 75