1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2015 Linaro 3*4882a593Smuzhiyun * Peter Griffin <peter.griffin@linaro.org> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __HI6553_PMIC_H__ 9*4882a593Smuzhiyun #define __HI6553_PMIC_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* Registers */ 12*4882a593Smuzhiyun enum { 13*4882a593Smuzhiyun HI6553_VERSION_REG = 0x000, 14*4882a593Smuzhiyun HI6553_ENABLE2_LDO1_8 = 0x029, 15*4882a593Smuzhiyun HI6553_DISABLE2_LDO1_8, 16*4882a593Smuzhiyun HI6553_ONOFF_STATUS2_LDO1_8, 17*4882a593Smuzhiyun HI6553_ENABLE3_LDO9_16, 18*4882a593Smuzhiyun HI6553_DISABLE3_LDO9_16, 19*4882a593Smuzhiyun HI6553_ONOFF_STATUS3_LDO9_16, 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun HI6553_DISABLE6_XO_CLK = 0x036, 22*4882a593Smuzhiyun HI6553_PERI_EN_MARK = 0x040, 23*4882a593Smuzhiyun HI6553_BUCK2_REG1 = 0x04a, 24*4882a593Smuzhiyun HI6553_BUCK2_REG5 = 0x04e, 25*4882a593Smuzhiyun HI6553_BUCK2_REG6, 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun HI6553_BUCK3_REG3 = 0x054, 28*4882a593Smuzhiyun HI6553_BUCK3_REG5 = 0x056, 29*4882a593Smuzhiyun HI6553_BUCK3_REG6, 30*4882a593Smuzhiyun HI6553_BUCK4_REG2 = 0x05b, 31*4882a593Smuzhiyun HI6553_BUCK4_REG5 = 0x05e, 32*4882a593Smuzhiyun HI6553_BUCK4_REG6, 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun HI6553_CLK_TOP0 = 0x063, 35*4882a593Smuzhiyun HI6553_CLK_TOP3 = 0x066, 36*4882a593Smuzhiyun HI6553_CLK_TOP4, 37*4882a593Smuzhiyun HI6553_VSET_BUCK2_ADJ = 0x06d, 38*4882a593Smuzhiyun HI6553_VSET_BUCK3_ADJ, 39*4882a593Smuzhiyun HI6553_LDO7_REG_ADJ = 0x078, 40*4882a593Smuzhiyun HI6553_LDO10_REG_ADJ = 0x07b, 41*4882a593Smuzhiyun HI6553_LDO19_REG_ADJ = 0x084, 42*4882a593Smuzhiyun HI6553_LDO20_REG_ADJ, 43*4882a593Smuzhiyun HI6553_DR_LED_CTRL = 0x098, 44*4882a593Smuzhiyun HI6553_DR_OUT_CTRL, 45*4882a593Smuzhiyun HI6553_DR3_ISET, 46*4882a593Smuzhiyun HI6553_DR3_START_DEL, 47*4882a593Smuzhiyun HI6553_DR4_ISET, 48*4882a593Smuzhiyun HI6553_DR4_START_DEL, 49*4882a593Smuzhiyun HI6553_DR345_TIM_CONF0 = 0x0a0, 50*4882a593Smuzhiyun HI6553_NP_REG_ADJ1 = 0x0be, 51*4882a593Smuzhiyun HI6553_NP_REG_CHG = 0x0c0, 52*4882a593Smuzhiyun HI6553_BUCK01_CTRL2 = 0x0d9, 53*4882a593Smuzhiyun HI6553_BUCK0_CTRL1 = 0x0dd, 54*4882a593Smuzhiyun HI6553_BUCK0_CTRL5 = 0x0e1, 55*4882a593Smuzhiyun HI6553_BUCK0_CTRL7 = 0x0e3, 56*4882a593Smuzhiyun HI6553_BUCK1_CTRL1 = 0x0e8, 57*4882a593Smuzhiyun HI6553_BUCK1_CTRL5 = 0x0ec, 58*4882a593Smuzhiyun HI6553_BUCK1_CTRL7 = 0x0ef, 59*4882a593Smuzhiyun HI6553_CLK19M2_600_586_EN = 0x0fe, 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define HI6553_DISABLE6_XO_CLK_BB (1 << 0) 63*4882a593Smuzhiyun #define HI6553_DISABLE6_XO_CLK_CONN (1 << 1) 64*4882a593Smuzhiyun #define HI6553_DISABLE6_XO_CLK_NFC (1 << 2) 65*4882a593Smuzhiyun #define HI6553_DISABLE6_XO_CLK_RF1 (1 << 3) 66*4882a593Smuzhiyun #define HI6553_DISABLE6_XO_CLK_RF2 (1 << 4) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define HI6553_LED_START_DELAY_TIME 0x00 69*4882a593Smuzhiyun #define HI6553_LED_ELEC_VALUE 0x07 70*4882a593Smuzhiyun #define HI6553_LED_LIGHT_TIME 0xf0 71*4882a593Smuzhiyun #define HI6553_LED_GREEN_ENABLE (1 << 1) 72*4882a593Smuzhiyun #define HI6553_LED_OUT_CTRL 0x00 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define HI6553_PMU_V300 0x30 75*4882a593Smuzhiyun #define HI6553_PMU_V310 0x31 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun int power_hi6553_init(u8 *base); 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #endif /* __HI6553_PMIC_H__ */ 80