1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2014 NVIDIA Corporation 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __POWER_AS3722_H__ 8*4882a593Smuzhiyun #define __POWER_AS3722_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define AS3722_GPIO_OUTPUT_VDDH (1 << 0) 11*4882a593Smuzhiyun #define AS3722_GPIO_INVERT (1 << 1) 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define AS3722_DEVICE_ID 0x0c 14*4882a593Smuzhiyun #define AS3722_SD_VOLTAGE(n) (0x00 + (n)) 15*4882a593Smuzhiyun #define AS3722_LDO_VOLTAGE(n) (0x10 + (n)) 16*4882a593Smuzhiyun #define AS3722_SD_CONTROL 0x4d 17*4882a593Smuzhiyun #define AS3722_LDO_CONTROL 0x4e 18*4882a593Smuzhiyun #define AS3722_ASIC_ID1 0x90 19*4882a593Smuzhiyun #define AS3722_ASIC_ID2 0x91 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define AS3722_GPIO_CONTROL(n) (0x08 + (n)) 22*4882a593Smuzhiyun #define AS3722_GPIO_SIGNAL_OUT 0x20 23*4882a593Smuzhiyun #define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH (1 << 0) 24*4882a593Smuzhiyun #define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL (7 << 0) 25*4882a593Smuzhiyun #define AS3722_GPIO_CONTROL_INVERT (1 << 7) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun int as3722_sd_set_voltage(struct udevice *dev, unsigned int sd, u8 value); 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #endif /* __POWER_AS3722_H__ */ 30