1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2012-2013
3*4882a593Smuzhiyun * Texas Instruments, <www.ti.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #ifndef PALMAS_H
8*4882a593Smuzhiyun #define PALMAS_H
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <i2c.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun /* I2C chip addresses, TW6035/37 */
14*4882a593Smuzhiyun #define TWL603X_CHIP_P1 0x48 /* Page 1 */
15*4882a593Smuzhiyun #define TWL603X_CHIP_P2 0x49 /* Page 2 */
16*4882a593Smuzhiyun #define TWL603X_CHIP_P3 0x4a /* Page 3 */
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /* TPS659038/39 */
19*4882a593Smuzhiyun #define TPS65903X_CHIP_P1 0x58 /* Page 1 */
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* Page 1 registers (0x1XY translates to page 1, reg addr 0xXY): */
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /* LDO1 control/voltage */
24*4882a593Smuzhiyun #define LDO1_CTRL 0x50
25*4882a593Smuzhiyun #define LDO1_VOLTAGE 0x51
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* LDO1 control/voltage for LP873x */
28*4882a593Smuzhiyun #define LP873X_LDO1_ADDR 0x60
29*4882a593Smuzhiyun #define LP873X_LDO1_CTRL 0x9
30*4882a593Smuzhiyun #define LP873X_LDO1_VOLTAGE 0xa
31*4882a593Smuzhiyun #define LP873X_LDO_VOLT_3V0 0x19
32*4882a593Smuzhiyun #define LP873X_LDO_VOLT_1V8 0xa
33*4882a593Smuzhiyun #define LP873X_LDO_CTRL_EN (0x1 << 0)
34*4882a593Smuzhiyun #define LP873X_LDO_CTRL_EN_PINCTRL (0x1 << 1)
35*4882a593Smuzhiyun #define LP873X_LDO_CTRL_RDIS_EN (0x1 << 2)
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* LDO2 control/voltage */
38*4882a593Smuzhiyun #define LDO2_CTRL 0x52
39*4882a593Smuzhiyun #define LDO2_VOLTAGE 0x53
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* LDO9 control/voltage */
42*4882a593Smuzhiyun #define LDO9_CTRL 0x60
43*4882a593Smuzhiyun #define LDO9_VOLTAGE 0x61
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* LDOUSB control/voltage */
46*4882a593Smuzhiyun #define LDOUSB_CTRL 0x64
47*4882a593Smuzhiyun #define LDOUSB_VOLTAGE 0x65
48*4882a593Smuzhiyun #define LDO_CTRL 0x6a
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* Control of 32 kHz audio clock */
51*4882a593Smuzhiyun #define CLK32KGAUDIO_CTRL 0xd5
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* SYSEN2_CTRL for VCC_3v3_AUX supply on the sEVM */
54*4882a593Smuzhiyun #define SYSEN2_CTRL 0xd9
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /*
57*4882a593Smuzhiyun * Bit field definitions for LDOx_CTRL, SYSENx_CTRL
58*4882a593Smuzhiyun * and some other xxx_CTRL resources:
59*4882a593Smuzhiyun */
60*4882a593Smuzhiyun #define LDO9_BYP_EN (1 << 6) /* LDO9 only! */
61*4882a593Smuzhiyun #define RSC_STAT_ON (1 << 4) /* RO status bit! */
62*4882a593Smuzhiyun #define RSC_MODE_SLEEP (1 << 2)
63*4882a593Smuzhiyun #define RSC_MODE_ACTIVE (1 << 0)
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* Some LDO voltage values */
66*4882a593Smuzhiyun #define LDO_VOLT_OFF 0
67*4882a593Smuzhiyun #define LDO_VOLT_1V8 0x13
68*4882a593Smuzhiyun #define LDO_VOLT_3V0 0x2b
69*4882a593Smuzhiyun #define LDO_VOLT_3V3 0x31
70*4882a593Smuzhiyun /* Request bypass, LDO9 only */
71*4882a593Smuzhiyun #define LDO9_BYPASS 0x3f
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* SMPS7_CTRL */
74*4882a593Smuzhiyun #define SMPS7_CTRL 0x30
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /* SMPS9_CTRL */
77*4882a593Smuzhiyun #define SMPS9_CTRL 0x38
78*4882a593Smuzhiyun #define SMPS9_VOLTAGE 0x3b
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /* SMPS10_CTRL */
81*4882a593Smuzhiyun #define SMPS10_CTRL 0x3c
82*4882a593Smuzhiyun #define SMPS10_MODE_ACTIVE_D 0x0d
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* Bit field definitions for SMPSx_CTRL */
85*4882a593Smuzhiyun #define SMPS_MODE_ACT_AUTO 1
86*4882a593Smuzhiyun #define SMPS_MODE_ACT_ECO 2
87*4882a593Smuzhiyun #define SMPS_MODE_ACT_FPWM 3
88*4882a593Smuzhiyun #define SMPS_MODE_SLP_AUTO (1 << 2)
89*4882a593Smuzhiyun #define SMPS_MODE_SLP_ECO (2 << 2)
90*4882a593Smuzhiyun #define SMPS_MODE_SLP_FPWM (3 << 2)
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /*
93*4882a593Smuzhiyun * Some popular SMPS voltages, all with RANGE=1; note
94*4882a593Smuzhiyun * that RANGE cannot be changed on the fly
95*4882a593Smuzhiyun */
96*4882a593Smuzhiyun #define SMPS_VOLT_OFF 0
97*4882a593Smuzhiyun #define SMPS_VOLT_1V2 0x90
98*4882a593Smuzhiyun #define SMPS_VOLT_1V8 0xae
99*4882a593Smuzhiyun #define SMPS_VOLT_2V1 0xbd
100*4882a593Smuzhiyun #define SMPS_VOLT_3V0 0xea
101*4882a593Smuzhiyun #define SMPS_VOLT_3V3 0xf9
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /* Backup Battery & VRTC Control */
104*4882a593Smuzhiyun #define BB_VRTC_CTRL 0xa8
105*4882a593Smuzhiyun /* Bit definitions for BB_VRTC_CTRL */
106*4882a593Smuzhiyun #define VRTC_EN_SLP (1 << 6)
107*4882a593Smuzhiyun #define VRTC_EN_OFF (1 << 5)
108*4882a593Smuzhiyun #define VRTC_PWEN (1 << 4)
109*4882a593Smuzhiyun #define BB_LOW_ICHRG (1 << 3)
110*4882a593Smuzhiyun #define BB_HIGH_ICHRG (0 << 3)
111*4882a593Smuzhiyun #define BB_VSEL_3V0 (0 << 1)
112*4882a593Smuzhiyun #define BB_VSEL_2V5 (1 << 1)
113*4882a593Smuzhiyun #define BB_VSEL_3V15 (2 << 1)
114*4882a593Smuzhiyun #define BB_VSEL_VBAT (3 << 1)
115*4882a593Smuzhiyun #define BB_CHRG_EN (1 << 0)
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /*
118*4882a593Smuzhiyun * Functions to read and write from TPS659038/TWL6035/TWL6037
119*4882a593Smuzhiyun * or other Palmas family of TI PMICs
120*4882a593Smuzhiyun */
palmas_i2c_write_u8(u8 chip_no,u8 reg,u8 val)121*4882a593Smuzhiyun static inline int palmas_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun return i2c_write(chip_no, reg, 1, &val, 1);
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
palmas_i2c_read_u8(u8 chip_no,u8 reg,u8 * val)126*4882a593Smuzhiyun static inline int palmas_i2c_read_u8(u8 chip_no, u8 reg, u8 *val)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun return i2c_read(chip_no, reg, 1, val, 1);
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun void palmas_init_settings(void);
132*4882a593Smuzhiyun int palmas_mmc1_poweron_ldo(uint voltage);
133*4882a593Smuzhiyun int lp873x_mmc1_poweron_ldo(uint voltage);
134*4882a593Smuzhiyun int twl603x_mmc1_set_ldo9(u8 vsel);
135*4882a593Smuzhiyun int twl603x_audio_power(u8 on);
136*4882a593Smuzhiyun int twl603x_enable_bb_charge(u8 bb_fields);
137*4882a593Smuzhiyun int palmas_enable_ss_ldo(void);
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun #endif /* PALMAS_H */
140