1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2012 3*4882a593Smuzhiyun * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __MV886352_H 9*4882a593Smuzhiyun #define __MV886352_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <common.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* PHY registers */ 14*4882a593Smuzhiyun #define PHY(itf) (itf) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define PHY_CTRL 0x00 17*4882a593Smuzhiyun #define PHY_100_MBPS 0x2000 18*4882a593Smuzhiyun #define PHY_1_GBPS 0x0040 19*4882a593Smuzhiyun #define AUTONEG_EN 0x1000 20*4882a593Smuzhiyun #define AUTONEG_RST 0x0200 21*4882a593Smuzhiyun #define FULL_DUPLEX 0x0100 22*4882a593Smuzhiyun #define PHY_PWR_DOWN 0x0800 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define PHY_STATUS 0x01 25*4882a593Smuzhiyun #define AN1000FIX 0x0001 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define PHY_SPEC_CTRL 0x10 28*4882a593Smuzhiyun #define SPEC_PWR_DOWN 0x0004 29*4882a593Smuzhiyun #define AUTO_MDIX_EN 0x0060 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define PHY_1000_CTRL 0x9 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define NO_ADV 0x0000 34*4882a593Smuzhiyun #define ADV_1000_FDPX 0x0200 35*4882a593Smuzhiyun #define ADV_1000_HDPX 0x0100 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define PHY_PAGE 0x16 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define AN1000FIX_PAGE 0x00fc 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* PORT or MAC registers */ 42*4882a593Smuzhiyun #define PORT(itf) (itf+0x10) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define PORT_STATUS 0x00 45*4882a593Smuzhiyun #define NO_PHY_DETECT 0x0000 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define PORT_PHY 0x01 48*4882a593Smuzhiyun #define RX_RGMII_TIM 0x8000 49*4882a593Smuzhiyun #define TX_RGMII_TIM 0x4000 50*4882a593Smuzhiyun #define FLOW_CTRL_EN 0x0080 51*4882a593Smuzhiyun #define FLOW_CTRL_FOR 0x0040 52*4882a593Smuzhiyun #define LINK_VAL 0x0020 53*4882a593Smuzhiyun #define LINK_FOR 0x0010 54*4882a593Smuzhiyun #define FULL_DPX 0x0008 55*4882a593Smuzhiyun #define FULL_DPX_FOR 0x0004 56*4882a593Smuzhiyun #define NO_SPEED_FOR 0x0003 57*4882a593Smuzhiyun #define SPEED_1000_FOR 0x0002 58*4882a593Smuzhiyun #define SPEED_100_FOR 0x0001 59*4882a593Smuzhiyun #define SPEED_10_FOR 0x0000 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define PORT_CTRL 0x04 62*4882a593Smuzhiyun #define FORWARDING 0x0003 63*4882a593Smuzhiyun #define EGRS_FLD_ALL 0x000c 64*4882a593Smuzhiyun #define PORT_DIS 0x0000 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun struct mv88e_sw_reg { 67*4882a593Smuzhiyun u8 port; 68*4882a593Smuzhiyun u8 reg; 69*4882a593Smuzhiyun u16 value; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun int mv88e_sw_reset(const char *devname, u8 phy_addr); 73*4882a593Smuzhiyun int mv88e_sw_program(const char *devname, u8 phy_addr, 74*4882a593Smuzhiyun struct mv88e_sw_reg *regs, int regs_nb); 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #endif 77