1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2013 Imagination Technologies 3*4882a593Smuzhiyun * Author: Paul Burton <paul.burton@imgtec.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __MSC01_H__ 9*4882a593Smuzhiyun #define __MSC01_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Bus Interface Unit 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define MSC01_BIU_IP1BAS1L_OFS 0x0208 16*4882a593Smuzhiyun #define MSC01_BIU_IP1MSK1L_OFS 0x0218 17*4882a593Smuzhiyun #define MSC01_BIU_IP1BAS2L_OFS 0x0248 18*4882a593Smuzhiyun #define MSC01_BIU_IP1MSK2L_OFS 0x0258 19*4882a593Smuzhiyun #define MSC01_BIU_IP2BAS1L_OFS 0x0288 20*4882a593Smuzhiyun #define MSC01_BIU_IP2MSK1L_OFS 0x0298 21*4882a593Smuzhiyun #define MSC01_BIU_IP2BAS2L_OFS 0x02c8 22*4882a593Smuzhiyun #define MSC01_BIU_IP2MSK2L_OFS 0x02d8 23*4882a593Smuzhiyun #define MSC01_BIU_IP3BAS1L_OFS 0x0308 24*4882a593Smuzhiyun #define MSC01_BIU_IP3MSK1L_OFS 0x0318 25*4882a593Smuzhiyun #define MSC01_BIU_IP3BAS2L_OFS 0x0348 26*4882a593Smuzhiyun #define MSC01_BIU_IP3MSK2L_OFS 0x0358 27*4882a593Smuzhiyun #define MSC01_BIU_MCBAS1L_OFS 0x0388 28*4882a593Smuzhiyun #define MSC01_BIU_MCMSK1L_OFS 0x0398 29*4882a593Smuzhiyun #define MSC01_BIU_MCBAS2L_OFS 0x03c8 30*4882a593Smuzhiyun #define MSC01_BIU_MCMSK2L_OFS 0x03d8 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* 33*4882a593Smuzhiyun * PCI Bridge 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define MSC01_PCI_SC2PMBASL_OFS 0x0208 37*4882a593Smuzhiyun #define MSC01_PCI_SC2PMMSKL_OFS 0x0218 38*4882a593Smuzhiyun #define MSC01_PCI_SC2PMMAPL_OFS 0x0228 39*4882a593Smuzhiyun #define MSC01_PCI_SC2PIOBASL_OFS 0x0248 40*4882a593Smuzhiyun #define MSC01_PCI_SC2PIOMSKL_OFS 0x0258 41*4882a593Smuzhiyun #define MSC01_PCI_SC2PIOMAPL_OFS 0x0268 42*4882a593Smuzhiyun #define MSC01_PCI_P2SCMSKL_OFS 0x0308 43*4882a593Smuzhiyun #define MSC01_PCI_P2SCMAPL_OFS 0x0318 44*4882a593Smuzhiyun #define MSC01_PCI_INTSTAT_OFS 0x0608 45*4882a593Smuzhiyun #define MSC01_PCI_CFGADDR_OFS 0x0610 46*4882a593Smuzhiyun #define MSC01_PCI_CFGDATA_OFS 0x0618 47*4882a593Smuzhiyun #define MSC01_PCI_HEAD0_OFS 0x2000 48*4882a593Smuzhiyun #define MSC01_PCI_HEAD1_OFS 0x2008 49*4882a593Smuzhiyun #define MSC01_PCI_HEAD2_OFS 0x2010 50*4882a593Smuzhiyun #define MSC01_PCI_HEAD3_OFS 0x2018 51*4882a593Smuzhiyun #define MSC01_PCI_HEAD4_OFS 0x2020 52*4882a593Smuzhiyun #define MSC01_PCI_HEAD5_OFS 0x2028 53*4882a593Smuzhiyun #define MSC01_PCI_HEAD6_OFS 0x2030 54*4882a593Smuzhiyun #define MSC01_PCI_HEAD7_OFS 0x2038 55*4882a593Smuzhiyun #define MSC01_PCI_HEAD8_OFS 0x2040 56*4882a593Smuzhiyun #define MSC01_PCI_HEAD9_OFS 0x2048 57*4882a593Smuzhiyun #define MSC01_PCI_HEAD10_OFS 0x2050 58*4882a593Smuzhiyun #define MSC01_PCI_HEAD11_OFS 0x2058 59*4882a593Smuzhiyun #define MSC01_PCI_HEAD12_OFS 0x2060 60*4882a593Smuzhiyun #define MSC01_PCI_HEAD13_OFS 0x2068 61*4882a593Smuzhiyun #define MSC01_PCI_HEAD14_OFS 0x2070 62*4882a593Smuzhiyun #define MSC01_PCI_HEAD15_OFS 0x2078 63*4882a593Smuzhiyun #define MSC01_PCI_BAR0_OFS 0x2220 64*4882a593Smuzhiyun #define MSC01_PCI_CFG_OFS 0x2380 65*4882a593Smuzhiyun #define MSC01_PCI_SWAP_OFS 0x2388 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define MSC01_PCI_SC2PMMSKL_MSK_MSK 0xff000000 68*4882a593Smuzhiyun #define MSC01_PCI_SC2PIOMSKL_MSK_MSK 0xff000000 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define MSC01_PCI_INTSTAT_TA_SHF 6 71*4882a593Smuzhiyun #define MSC01_PCI_INTSTAT_TA_MSK (0x1 << MSC01_PCI_INTSTAT_TA_SHF) 72*4882a593Smuzhiyun #define MSC01_PCI_INTSTAT_MA_SHF 7 73*4882a593Smuzhiyun #define MSC01_PCI_INTSTAT_MA_MSK (0x1 << MSC01_PCI_INTSTAT_MA_SHF) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define MSC01_PCI_CFGADDR_BNUM_SHF 16 76*4882a593Smuzhiyun #define MSC01_PCI_CFGADDR_BNUM_MSK (0xff << MSC01_PCI_CFGADDR_BNUM_SHF) 77*4882a593Smuzhiyun #define MSC01_PCI_CFGADDR_DNUM_SHF 11 78*4882a593Smuzhiyun #define MSC01_PCI_CFGADDR_DNUM_MSK (0x1f << MSC01_PCI_CFGADDR_DNUM_SHF) 79*4882a593Smuzhiyun #define MSC01_PCI_CFGADDR_FNUM_SHF 8 80*4882a593Smuzhiyun #define MSC01_PCI_CFGADDR_FNUM_MSK (0x3 << MSC01_PCI_CFGADDR_FNUM_SHF) 81*4882a593Smuzhiyun #define MSC01_PCI_CFGADDR_RNUM_SHF 2 82*4882a593Smuzhiyun #define MSC01_PCI_CFGADDR_RNUM_MSK (0x3f << MSC01_PCI_CFGADDR_RNUM_SHF) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define MSC01_PCI_HEAD0_VENDORID_SHF 0 85*4882a593Smuzhiyun #define MSC01_PCI_HEAD0_DEVICEID_SHF 16 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define MSC01_PCI_HEAD2_REV_SHF 0 88*4882a593Smuzhiyun #define MSC01_PCI_HEAD2_CLASS_SHF 16 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define MSC01_PCI_CFG_EN_SHF 15 91*4882a593Smuzhiyun #define MSC01_PCI_CFG_EN_MSK (0x1 << MSC01_PCI_CFG_EN_SHF) 92*4882a593Smuzhiyun #define MSC01_PCI_CFG_G_SHF 16 93*4882a593Smuzhiyun #define MSC01_PCI_CFG_G_MSK (0x1 << MSC01_PCI_CFG_G_SHF) 94*4882a593Smuzhiyun #define MSC01_PCI_CFG_RA_SHF 17 95*4882a593Smuzhiyun #define MSC01_PCI_CFG_RA_MSK (0x1 << MSC01_PCI_CFG_RA_SHF) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define MSC01_PCI_SWAP_BAR0_BSWAP_SHF 0 98*4882a593Smuzhiyun #define MSC01_PCI_SWAP_IO_BSWAP_SHF 18 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* 101*4882a593Smuzhiyun * Peripheral Bus Controller 102*4882a593Smuzhiyun */ 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define MSC01_PBC_CLKCFG_OFS 0x0100 105*4882a593Smuzhiyun #define MSC01_PBC_CS0CFG_OFS 0x0400 106*4882a593Smuzhiyun #define MSC01_PBC_CS0TIM_OFS 0x0500 107*4882a593Smuzhiyun #define MSC01_PBC_CS0RW_OFS 0x0600 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define MSC01_PBC_CLKCFG_SHF 0 110*4882a593Smuzhiyun #define MSC01_PBC_CLKCFG_MSK (0x1f << MSC01_PBC_CLKCFG_SHF) 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define MSC01_PBC_CS0CFG_WS_SHF 0 113*4882a593Smuzhiyun #define MSC01_PBC_CS0CFG_WS_MSK (0x1f << MSC01_PBC_CS0CFG_WS_SHF) 114*4882a593Smuzhiyun #define MSC01_PBC_CS0CFG_WSIDLE_SHF 8 115*4882a593Smuzhiyun #define MSC01_PBC_CS0CFG_WSIDLE_MSK (0x1f << MSC01_PBC_CS0CFG_WSIDLE_SHF) 116*4882a593Smuzhiyun #define MSC01_PBC_CS0CFG_DTYP_SHF 16 117*4882a593Smuzhiyun #define MSC01_PBC_CS0CFG_DTYP_MSK (0x3 << MSC01_PBC_CS0CFG_DTYP_SHF) 118*4882a593Smuzhiyun #define MSC01_PBC_CS0CFG_ADM_SHF 20 119*4882a593Smuzhiyun #define MSC01_PBC_CS0CFG_ADM_MSK (0x1 << MSC01_PBC_CS0CFG_ADM_SHF) 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define MSC01_PBC_CS0TIM_CAT_SHF 0 122*4882a593Smuzhiyun #define MSC01_PBC_CS0TIM_CAT_MSK (0x1f << MSC01_PBC_CS0TIM_CAT_SHF) 123*4882a593Smuzhiyun #define MSC01_PBC_CS0TIM_CDT_SHF 8 124*4882a593Smuzhiyun #define MSC01_PBC_CS0TIM_CDT_MSK (0x1f << MSC01_PBC_CS0TIM_CDT_SHF) 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define MSC01_PBC_CS0RW_WAT_SHF 0 127*4882a593Smuzhiyun #define MSC01_PBC_CS0RW_WAT_MSK (0x1f << MSC01_PBC_CS0RW_WAT_SHF) 128*4882a593Smuzhiyun #define MSC01_PBC_CS0RW_WDT_SHF 8 129*4882a593Smuzhiyun #define MSC01_PBC_CS0RW_WDT_MSK (0x1f << MSC01_PBC_CS0RW_WDT_SHF) 130*4882a593Smuzhiyun #define MSC01_PBC_CS0RW_RAT_SHF 16 131*4882a593Smuzhiyun #define MSC01_PBC_CS0RW_RAT_MSK (0x1f << MSC01_PBC_CS0RW_RAT_SHF) 132*4882a593Smuzhiyun #define MSC01_PBC_CS0RW_RDT_SHF 24 133*4882a593Smuzhiyun #define MSC01_PBC_CS0RW_RDT_MSK (0x1f << MSC01_PBC_CS0RW_RDT_SHF) 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #endif /* __MSC01_H__ */ 136