1*4882a593Smuzhiyun #ifndef _MPC8XX_IRQ_H 2*4882a593Smuzhiyun #define _MPC8XX_IRQ_H 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* The MPC8xx cores have 16 possible interrupts. There are eight 5*4882a593Smuzhiyun * possible level sensitive interrupts assigned and generated internally 6*4882a593Smuzhiyun * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer. 7*4882a593Smuzhiyun * There are eight external interrupts (IRQs) that can be configured 8*4882a593Smuzhiyun * as either level or edge sensitive. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * On some implementations, there is also the possibility of an 8259 11*4882a593Smuzhiyun * through the PCI and PCI-ISA bridges. 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * We don't support the 8259 (yet). 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #define NR_SIU_INTS 16 16*4882a593Smuzhiyun #define NR_8259_INTS 0 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define NR_IRQS (NR_SIU_INTS + NR_8259_INTS) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* These values must be zero-based and map 1:1 with the SIU configuration. 21*4882a593Smuzhiyun * They are used throughout the 8xx I/O subsystem to generate 22*4882a593Smuzhiyun * interrupt masks, flags, and other control patterns. This is why the 23*4882a593Smuzhiyun * current kernel assumption of the 8259 as the base controller is such 24*4882a593Smuzhiyun * a pain in the butt. 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun #define SIU_IRQ0 (0) /* Highest priority */ 27*4882a593Smuzhiyun #define SIU_LEVEL0 (1) 28*4882a593Smuzhiyun #define SIU_IRQ1 (2) 29*4882a593Smuzhiyun #define SIU_LEVEL1 (3) 30*4882a593Smuzhiyun #define SIU_IRQ2 (4) 31*4882a593Smuzhiyun #define SIU_LEVEL2 (5) 32*4882a593Smuzhiyun #define SIU_IRQ3 (6) 33*4882a593Smuzhiyun #define SIU_LEVEL3 (7) 34*4882a593Smuzhiyun #define SIU_IRQ4 (8) 35*4882a593Smuzhiyun #define SIU_LEVEL4 (9) 36*4882a593Smuzhiyun #define SIU_IRQ5 (10) 37*4882a593Smuzhiyun #define SIU_LEVEL5 (11) 38*4882a593Smuzhiyun #define SIU_IRQ6 (12) 39*4882a593Smuzhiyun #define SIU_LEVEL6 (13) 40*4882a593Smuzhiyun #define SIU_IRQ7 (14) 41*4882a593Smuzhiyun #define SIU_LEVEL7 (15) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* The internal interrupts we can configure as we see fit. 44*4882a593Smuzhiyun * My personal preference is CPM at level 2, which puts it above the 45*4882a593Smuzhiyun * MBX PCI/ISA/IDE interrupts. 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #ifdef CONFIG_SYS_CPM_INTERRUPT 49*4882a593Smuzhiyun # define CPM_INTERRUPT CONFIG_SYS_CPM_INTERRUPT 50*4882a593Smuzhiyun #else 51*4882a593Smuzhiyun # define CPM_INTERRUPT SIU_LEVEL2 52*4882a593Smuzhiyun #endif 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Some internal interrupt registers use an 8-bit mask for the interrupt 55*4882a593Smuzhiyun * level instead of a number. 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun #define mk_int_int_mask(IL) (1 << (7 - (IL/2))) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #endif /* _MPC8XX_IRQ_H */ 60