1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2000-2004 3*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* 9*4882a593Smuzhiyun * mpc8xx.h 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * MPC8xx specific definitions 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef __MPCXX_H__ 15*4882a593Smuzhiyun #define __MPCXX_H__ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /*----------------------------------------------------------------------- 19*4882a593Smuzhiyun * Exception offsets (PowerPC standard) 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ 22*4882a593Smuzhiyun #define _START_OFFSET EXC_OFF_SYS_RESET 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /*----------------------------------------------------------------------- 25*4882a593Smuzhiyun * SYPCR - System Protection Control Register 11-9 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun #define SYPCR_SWTC 0xFFFF0000 /* Software Watchdog Timer Count */ 28*4882a593Smuzhiyun #define SYPCR_BMT 0x0000FF00 /* Bus Monitor Timing */ 29*4882a593Smuzhiyun #define SYPCR_BME 0x00000080 /* Bus Monitor Enable */ 30*4882a593Smuzhiyun #define SYPCR_SWF 0x00000008 /* Software Watchdog Freeze */ 31*4882a593Smuzhiyun #define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */ 32*4882a593Smuzhiyun #define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select */ 33*4882a593Smuzhiyun #define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /*----------------------------------------------------------------------- 36*4882a593Smuzhiyun * SIUMCR - SIU Module Configuration Register 11-6 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun #define SIUMCR_EARB 0x80000000 /* External Arbitration */ 39*4882a593Smuzhiyun #define SIUMCR_EARP0 0x00000000 /* External Arbi. Request priority 0 */ 40*4882a593Smuzhiyun #define SIUMCR_EARP1 0x10000000 /* External Arbi. Request priority 1 */ 41*4882a593Smuzhiyun #define SIUMCR_EARP2 0x20000000 /* External Arbi. Request priority 2 */ 42*4882a593Smuzhiyun #define SIUMCR_EARP3 0x30000000 /* External Arbi. Request priority 3 */ 43*4882a593Smuzhiyun #define SIUMCR_EARP4 0x40000000 /* External Arbi. Request priority 4 */ 44*4882a593Smuzhiyun #define SIUMCR_EARP5 0x50000000 /* External Arbi. Request priority 5 */ 45*4882a593Smuzhiyun #define SIUMCR_EARP6 0x60000000 /* External Arbi. Request priority 6 */ 46*4882a593Smuzhiyun #define SIUMCR_EARP7 0x70000000 /* External Arbi. Request priority 7 */ 47*4882a593Smuzhiyun #define SIUMCR_DSHW 0x00800000 /* Data Showcycles */ 48*4882a593Smuzhiyun #define SIUMCR_DBGC00 0x00000000 /* Debug pins configuration */ 49*4882a593Smuzhiyun #define SIUMCR_DBGC01 0x00200000 /* - " - */ 50*4882a593Smuzhiyun #define SIUMCR_DBGC10 0x00400000 /* - " - */ 51*4882a593Smuzhiyun #define SIUMCR_DBGC11 0x00600000 /* - " - */ 52*4882a593Smuzhiyun #define SIUMCR_DBPC00 0x00000000 /* Debug Port pins Config. */ 53*4882a593Smuzhiyun #define SIUMCR_DBPC01 0x00080000 /* - " - */ 54*4882a593Smuzhiyun #define SIUMCR_DBPC10 0x00100000 /* - " - */ 55*4882a593Smuzhiyun #define SIUMCR_DBPC11 0x00180000 /* - " - */ 56*4882a593Smuzhiyun #define SIUMCR_FRC 0x00020000 /* FRZ pin Configuration */ 57*4882a593Smuzhiyun #define SIUMCR_DLK 0x00010000 /* Debug Register Lock */ 58*4882a593Smuzhiyun #define SIUMCR_PNCS 0x00008000 /* Parity Non-mem Crtl reg */ 59*4882a593Smuzhiyun #define SIUMCR_OPAR 0x00004000 /* Odd Parity */ 60*4882a593Smuzhiyun #define SIUMCR_DPC 0x00002000 /* Data Parity pins Config. */ 61*4882a593Smuzhiyun #define SIUMCR_MPRE 0x00001000 /* Multi CPU Reserva. Enable */ 62*4882a593Smuzhiyun #define SIUMCR_MLRC00 0x00000000 /* Multi Level Reserva. Ctrl */ 63*4882a593Smuzhiyun #define SIUMCR_MLRC01 0x00000400 /* - " - */ 64*4882a593Smuzhiyun #define SIUMCR_MLRC10 0x00000800 /* - " - */ 65*4882a593Smuzhiyun #define SIUMCR_MLRC11 0x00000C00 /* - " - */ 66*4882a593Smuzhiyun #define SIUMCR_AEME 0x00000200 /* Asynchro External Master */ 67*4882a593Smuzhiyun #define SIUMCR_SEME 0x00000100 /* Synchro External Master */ 68*4882a593Smuzhiyun #define SIUMCR_BSC 0x00000080 /* Byte Select Configuration */ 69*4882a593Smuzhiyun #define SIUMCR_GB5E 0x00000040 /* GPL_B(5) Enable */ 70*4882a593Smuzhiyun #define SIUMCR_B2DD 0x00000020 /* Bank 2 Double Drive */ 71*4882a593Smuzhiyun #define SIUMCR_B3DD 0x00000010 /* Bank 3 Double Drive */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /*----------------------------------------------------------------------- 74*4882a593Smuzhiyun * TBSCR - Time Base Status and Control Register 11-26 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun #define TBSCR_TBIRQ7 0x8000 /* Time Base Interrupt Request 7 */ 77*4882a593Smuzhiyun #define TBSCR_TBIRQ6 0x4000 /* Time Base Interrupt Request 6 */ 78*4882a593Smuzhiyun #define TBSCR_TBIRQ5 0x2000 /* Time Base Interrupt Request 5 */ 79*4882a593Smuzhiyun #define TBSCR_TBIRQ4 0x1000 /* Time Base Interrupt Request 4 */ 80*4882a593Smuzhiyun #define TBSCR_TBIRQ3 0x0800 /* Time Base Interrupt Request 3 */ 81*4882a593Smuzhiyun #define TBSCR_TBIRQ2 0x0400 /* Time Base Interrupt Request 2 */ 82*4882a593Smuzhiyun #define TBSCR_TBIRQ1 0x0200 /* Time Base Interrupt Request 1 */ 83*4882a593Smuzhiyun #define TBSCR_TBIRQ0 0x0100 /* Time Base Interrupt Request 0 */ 84*4882a593Smuzhiyun #if 0 /* already in asm/immap_8xx.h */ 85*4882a593Smuzhiyun #define TBSCR_REFA 0x0080 /* Reference Interrupt Status A */ 86*4882a593Smuzhiyun #define TBSCR_REFB 0x0040 /* Reference Interrupt Status B */ 87*4882a593Smuzhiyun #define TBSCR_REFAE 0x0008 /* Second Interrupt Enable A */ 88*4882a593Smuzhiyun #define TBSCR_REFBE 0x0004 /* Second Interrupt Enable B */ 89*4882a593Smuzhiyun #define TBSCR_TBF 0x0002 /* Time Base Freeze */ 90*4882a593Smuzhiyun #define TBSCR_TBE 0x0001 /* Time Base Enable */ 91*4882a593Smuzhiyun #endif 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /*----------------------------------------------------------------------- 94*4882a593Smuzhiyun * PISCR - Periodic Interrupt Status and Control Register 11-31 95*4882a593Smuzhiyun */ 96*4882a593Smuzhiyun #undef PISCR_PIRQ /* TBD */ 97*4882a593Smuzhiyun #define PISCR_PITF 0x0002 /* Periodic Interrupt Timer Freeze */ 98*4882a593Smuzhiyun #if 0 /* already in asm/immap_8xx.h */ 99*4882a593Smuzhiyun #define PISCR_PS 0x0080 /* Periodic interrupt Status */ 100*4882a593Smuzhiyun #define PISCR_PIE 0x0004 /* Periodic Interrupt Enable */ 101*4882a593Smuzhiyun #define PISCR_PTE 0x0001 /* Periodic Timer Enable */ 102*4882a593Smuzhiyun #endif 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /*----------------------------------------------------------------------- 105*4882a593Smuzhiyun * RSR - Reset Status Register 5-4 106*4882a593Smuzhiyun */ 107*4882a593Smuzhiyun #define RSR_JTRS 0x01000000 /* JTAG Reset Status */ 108*4882a593Smuzhiyun #define RSR_DBSRS 0x02000000 /* Debug Port Soft Reset Status */ 109*4882a593Smuzhiyun #define RSR_DBHRS 0x04000000 /* Debug Port Hard Reset Status */ 110*4882a593Smuzhiyun #define RSR_CSRS 0x08000000 /* Check Stop Reset Status */ 111*4882a593Smuzhiyun #define RSR_SWRS 0x10000000 /* Software Watchdog Reset Status*/ 112*4882a593Smuzhiyun #define RSR_LLRS 0x20000000 /* Loss-of-Lock Reset Status */ 113*4882a593Smuzhiyun #define RSR_ESRS 0x40000000 /* External Soft Reset Status */ 114*4882a593Smuzhiyun #define RSR_EHRS 0x80000000 /* External Hard Reset Status */ 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #define RSR_ALLBITS (RSR_JTRS|RSR_DBSRS|RSR_DBHRS|RSR_CSRS|RSR_SWRS|RSR_LLRS|RSR_ESRS|RSR_EHRS) 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /*----------------------------------------------------------------------- 119*4882a593Smuzhiyun * Newer chips (MPC866 family and MPC87x/88x family) have different 120*4882a593Smuzhiyun * clock distribution system. Their IMMR lower half is >= 0x0800 121*4882a593Smuzhiyun */ 122*4882a593Smuzhiyun #define MPC8xx_NEW_CLK 0x0800 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /*----------------------------------------------------------------------- 125*4882a593Smuzhiyun * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 126*4882a593Smuzhiyun */ 127*4882a593Smuzhiyun /* Newer chips (MPC866/87x/88x et al) defines */ 128*4882a593Smuzhiyun #define PLPRCR_MFN_MSK 0xF8000000 /* Multiplication factor numerator bits */ 129*4882a593Smuzhiyun #define PLPRCR_MFN_SHIFT 27 /* Multiplication factor numerator shift*/ 130*4882a593Smuzhiyun #define PLPRCR_MFD_MSK 0x07C00000 /* Multiplication factor denominator bits */ 131*4882a593Smuzhiyun #define PLPRCR_MFD_SHIFT 22 /* Multiplication factor denominator shift*/ 132*4882a593Smuzhiyun #define PLPRCR_S_MSK 0x00300000 /* Multiplication factor integer bits */ 133*4882a593Smuzhiyun #define PLPRCR_S_SHIFT 20 /* Multiplication factor integer shift */ 134*4882a593Smuzhiyun #define PLPRCR_MFI_MSK 0x000F0000 /* Multiplication factor integer bits */ 135*4882a593Smuzhiyun #define PLPRCR_MFI_SHIFT 16 /* Multiplication factor integer shift */ 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #define PLPRCR_PDF_MSK 0x0000001E /* Predivision Factor bits */ 138*4882a593Smuzhiyun #define PLPRCR_PDF_SHIFT 1 /* Predivision Factor shift value */ 139*4882a593Smuzhiyun #define PLPRCR_DBRMO 0x00000001 /* DPLL BRM Order bit */ 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun /* Multiplication factor + PDF bits */ 142*4882a593Smuzhiyun #define PLPRCR_MFACT_MSK (PLPRCR_MFN_MSK | \ 143*4882a593Smuzhiyun PLPRCR_MFD_MSK | \ 144*4882a593Smuzhiyun PLPRCR_S_MSK | \ 145*4882a593Smuzhiyun PLPRCR_MFI_MSK | \ 146*4882a593Smuzhiyun PLPRCR_PDF_MSK) 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* Common defines */ 149*4882a593Smuzhiyun #define PLPRCR_TEXPS 0x00004000 /* TEXP Status */ 150*4882a593Smuzhiyun #define PLPRCR_CSRC 0x00000400 /* Clock Source */ 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun #define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */ 153*4882a593Smuzhiyun #define PLPRCR_LOLRE 0x00000040 /* Loss Of Lock Reset Enable */ 154*4882a593Smuzhiyun #define PLPRCR_FIOPD 0x00000020 /* Force I/O Pull Down */ 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /*----------------------------------------------------------------------- 157*4882a593Smuzhiyun * SCCR - System Clock and reset Control Register 15-27 158*4882a593Smuzhiyun */ 159*4882a593Smuzhiyun #define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */ 160*4882a593Smuzhiyun #define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */ 161*4882a593Smuzhiyun #define SCCR_COM10 0x40000000 /* reserved */ 162*4882a593Smuzhiyun #define SCCR_COM11 0x60000000 /* CLKOUT output buffer disabled */ 163*4882a593Smuzhiyun #define SCCR_TBS 0x02000000 /* Time Base Source */ 164*4882a593Smuzhiyun #define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */ 165*4882a593Smuzhiyun #define SCCR_RTSEL 0x00800000 /* RTC circuit input source select */ 166*4882a593Smuzhiyun #define SCCR_CRQEN 0x00400000 /* CPM Request Enable */ 167*4882a593Smuzhiyun #define SCCR_PRQEN 0x00200000 /* Power Management Request Enable */ 168*4882a593Smuzhiyun #define SCCR_EBDF00 0x00000000 /* CLKOUT is GCLK2 / 1 (normal op.) */ 169*4882a593Smuzhiyun #define SCCR_EBDF01 0x00020000 /* CLKOUT is GCLK2 / 2 */ 170*4882a593Smuzhiyun #define SCCR_EBDF10 0x00040000 /* reserved */ 171*4882a593Smuzhiyun #define SCCR_EBDF11 0x00060000 /* reserved */ 172*4882a593Smuzhiyun #define SCCR_DFSYNC00 0x00000000 /* SyncCLK division by 1 (normal op.) */ 173*4882a593Smuzhiyun #define SCCR_DFSYNC01 0x00002000 /* SyncCLK division by 4 */ 174*4882a593Smuzhiyun #define SCCR_DFSYNC10 0x00004000 /* SyncCLK division by 16 */ 175*4882a593Smuzhiyun #define SCCR_DFSYNC11 0x00006000 /* SyncCLK division by 64 */ 176*4882a593Smuzhiyun #define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 1 (normal op.) */ 177*4882a593Smuzhiyun #define SCCR_DFBRG01 0x00000800 /* BRGCLK division by 4 */ 178*4882a593Smuzhiyun #define SCCR_DFBRG10 0x00001000 /* BRGCLK division by 16 */ 179*4882a593Smuzhiyun #define SCCR_DFBRG11 0x00001800 /* BRGCLK division by 64 */ 180*4882a593Smuzhiyun #define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */ 181*4882a593Smuzhiyun #define SCCR_DFNL001 0x00000100 /* Division by 4 */ 182*4882a593Smuzhiyun #define SCCR_DFNL010 0x00000200 /* Division by 8 */ 183*4882a593Smuzhiyun #define SCCR_DFNL011 0x00000300 /* Division by 16 */ 184*4882a593Smuzhiyun #define SCCR_DFNL100 0x00000400 /* Division by 32 */ 185*4882a593Smuzhiyun #define SCCR_DFNL101 0x00000500 /* Division by 64 */ 186*4882a593Smuzhiyun #define SCCR_DFNL110 0x00000600 /* Division by 128 */ 187*4882a593Smuzhiyun #define SCCR_DFNL111 0x00000700 /* Division by 256 (maximum) */ 188*4882a593Smuzhiyun #define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */ 189*4882a593Smuzhiyun #define SCCR_DFNH110 0x000000D0 /* Division by 64 (maximum) */ 190*4882a593Smuzhiyun #define SCCR_DFNH111 0x000000E0 /* reserved */ 191*4882a593Smuzhiyun #define SCCR_DFLCD000 0x00000000 /* Division by 1 (default = minimum) */ 192*4882a593Smuzhiyun #define SCCR_DFLCD001 0x00000004 /* Division by 2 */ 193*4882a593Smuzhiyun #define SCCR_DFLCD010 0x00000008 /* Division by 4 */ 194*4882a593Smuzhiyun #define SCCR_DFLCD011 0x0000000C /* Division by 8 */ 195*4882a593Smuzhiyun #define SCCR_DFLCD100 0x00000010 /* Division by 16 */ 196*4882a593Smuzhiyun #define SCCR_DFLCD101 0x00000014 /* Division by 32 */ 197*4882a593Smuzhiyun #define SCCR_DFLCD110 0x00000018 /* Division by 64 (maximum) */ 198*4882a593Smuzhiyun #define SCCR_DFLCD111 0x0000001C /* reserved */ 199*4882a593Smuzhiyun #define SCCR_DFALCD00 0x00000000 /* Division by 1 (default = minimum) */ 200*4882a593Smuzhiyun #define SCCR_DFALCD01 0x00000001 /* Division by 3 */ 201*4882a593Smuzhiyun #define SCCR_DFALCD10 0x00000002 /* Division by 5 */ 202*4882a593Smuzhiyun #define SCCR_DFALCD11 0x00000003 /* Division by 7 (maximum) */ 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun /*----------------------------------------------------------------------- 206*4882a593Smuzhiyun * BR - Memory Controler: Base Register 16-9 207*4882a593Smuzhiyun */ 208*4882a593Smuzhiyun #define BR_BA_MSK 0xFFFF8000 /* Base Address Mask */ 209*4882a593Smuzhiyun #define BR_AT_MSK 0x00007000 /* Address Type Mask */ 210*4882a593Smuzhiyun #define BR_PS_MSK 0x00000C00 /* Port Size Mask */ 211*4882a593Smuzhiyun #define BR_PS_32 0x00000000 /* 32 bit port size */ 212*4882a593Smuzhiyun #define BR_PS_16 0x00000800 /* 16 bit port size */ 213*4882a593Smuzhiyun #define BR_PS_8 0x00000400 /* 8 bit port size */ 214*4882a593Smuzhiyun #define BR_PARE 0x00000200 /* Parity Enable */ 215*4882a593Smuzhiyun #define BR_WP 0x00000100 /* Write Protect */ 216*4882a593Smuzhiyun #define BR_MS_MSK 0x000000C0 /* Machine Select Mask */ 217*4882a593Smuzhiyun #define BR_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */ 218*4882a593Smuzhiyun #define BR_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */ 219*4882a593Smuzhiyun #define BR_MS_UPMB 0x000000C0 /* U.P.M.B Machine Select */ 220*4882a593Smuzhiyun #define BR_V 0x00000001 /* Bank Valid */ 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun /*----------------------------------------------------------------------- 223*4882a593Smuzhiyun * OR - Memory Controler: Option Register 16-11 224*4882a593Smuzhiyun */ 225*4882a593Smuzhiyun #define OR_AM_MSK 0xFFFF8000 /* Address Mask Mask */ 226*4882a593Smuzhiyun #define OR_ATM_MSK 0x00007000 /* Address Type Mask Mask */ 227*4882a593Smuzhiyun #define OR_CSNT_SAM 0x00000800 /* Chip Select Negation Time/ Start */ 228*4882a593Smuzhiyun /* Address Multiplex */ 229*4882a593Smuzhiyun #define OR_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask */ 230*4882a593Smuzhiyun #define OR_ACS_DIV1 0x00000000 /* CS is output at the same time */ 231*4882a593Smuzhiyun #define OR_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later */ 232*4882a593Smuzhiyun #define OR_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later */ 233*4882a593Smuzhiyun #define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */ 234*4882a593Smuzhiyun #define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/ 235*4882a593Smuzhiyun #define OR_BI 0x00000100 /* Burst inhibit */ 236*4882a593Smuzhiyun #define OR_SCY_MSK 0x000000F0 /* Cycle Lenght in Clocks */ 237*4882a593Smuzhiyun #define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */ 238*4882a593Smuzhiyun #define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */ 239*4882a593Smuzhiyun #define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */ 240*4882a593Smuzhiyun #define OR_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */ 241*4882a593Smuzhiyun #define OR_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */ 242*4882a593Smuzhiyun #define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */ 243*4882a593Smuzhiyun #define OR_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */ 244*4882a593Smuzhiyun #define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ 245*4882a593Smuzhiyun #define OR_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */ 246*4882a593Smuzhiyun #define OR_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */ 247*4882a593Smuzhiyun #define OR_SCY_10_CLK 0x000000A0 /* 10 clock cycles wait states */ 248*4882a593Smuzhiyun #define OR_SCY_11_CLK 0x000000B0 /* 11 clock cycles wait states */ 249*4882a593Smuzhiyun #define OR_SCY_12_CLK 0x000000C0 /* 12 clock cycles wait states */ 250*4882a593Smuzhiyun #define OR_SCY_13_CLK 0x000000D0 /* 13 clock cycles wait states */ 251*4882a593Smuzhiyun #define OR_SCY_14_CLK 0x000000E0 /* 14 clock cycles wait states */ 252*4882a593Smuzhiyun #define OR_SCY_15_CLK 0x000000F0 /* 15 clock cycles wait states */ 253*4882a593Smuzhiyun #define OR_SETA 0x00000008 /* External Transfer Acknowledge */ 254*4882a593Smuzhiyun #define OR_TRLX 0x00000004 /* Timing Relaxed */ 255*4882a593Smuzhiyun #define OR_EHTR 0x00000002 /* Extended Hold Time on Read */ 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun /*----------------------------------------------------------------------- 259*4882a593Smuzhiyun * MPTPR - Memory Periodic Timer Prescaler Register 16-17 260*4882a593Smuzhiyun */ 261*4882a593Smuzhiyun #define MPTPR_PTP_MSK 0xFF00 /* Periodic Timers Prescaler Mask */ 262*4882a593Smuzhiyun #define MPTPR_PTP_DIV2 0x2000 /* BRGCLK divided by 2 */ 263*4882a593Smuzhiyun #define MPTPR_PTP_DIV4 0x1000 /* BRGCLK divided by 4 */ 264*4882a593Smuzhiyun #define MPTPR_PTP_DIV8 0x0800 /* BRGCLK divided by 8 */ 265*4882a593Smuzhiyun #define MPTPR_PTP_DIV16 0x0400 /* BRGCLK divided by 16 */ 266*4882a593Smuzhiyun #define MPTPR_PTP_DIV32 0x0200 /* BRGCLK divided by 32 */ 267*4882a593Smuzhiyun #define MPTPR_PTP_DIV64 0x0100 /* BRGCLK divided by 64 */ 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun /*----------------------------------------------------------------------- 270*4882a593Smuzhiyun * MCR - Memory Command Register 271*4882a593Smuzhiyun */ 272*4882a593Smuzhiyun #define MCR_OP_WRITE 0x00000000 /* WRITE command */ 273*4882a593Smuzhiyun #define MCR_OP_READ 0x40000000 /* READ command */ 274*4882a593Smuzhiyun #define MCR_OP_RUN 0x80000000 /* RUN command */ 275*4882a593Smuzhiyun #define MCR_UPM_A 0x00000000 /* Select UPM A */ 276*4882a593Smuzhiyun #define MCR_UPM_B 0x00800000 /* Select UPM B */ 277*4882a593Smuzhiyun #define MCR_MB_CS0 0x00000000 /* Use Chip Select /CS0 */ 278*4882a593Smuzhiyun #define MCR_MB_CS1 0x00002000 /* Use Chip Select /CS1 */ 279*4882a593Smuzhiyun #define MCR_MB_CS2 0x00004000 /* Use Chip Select /CS2 */ 280*4882a593Smuzhiyun #define MCR_MB_CS3 0x00006000 /* Use Chip Select /CS3 */ 281*4882a593Smuzhiyun #define MCR_MB_CS4 0x00008000 /* Use Chip Select /CS4 */ 282*4882a593Smuzhiyun #define MCR_MB_CS5 0x0000A000 /* Use Chip Select /CS5 */ 283*4882a593Smuzhiyun #define MCR_MB_CS6 0x0000C000 /* Use Chip Select /CS6 */ 284*4882a593Smuzhiyun #define MCR_MB_CS7 0x0000E000 /* Use Chip Select /CS7 */ 285*4882a593Smuzhiyun #define MCR_MLCF(n) (((n)&0xF)<<8) /* Memory Command Loop Count Field */ 286*4882a593Smuzhiyun #define MCR_MAD(addr) ((addr)&0x3F) /* Memory Array Index */ 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun /*----------------------------------------------------------------------- 289*4882a593Smuzhiyun * Machine A Mode Register 16-13 290*4882a593Smuzhiyun */ 291*4882a593Smuzhiyun #define MAMR_PTA_MSK 0xFF000000 /* Periodic Timer A period mask */ 292*4882a593Smuzhiyun #define MAMR_PTA_SHIFT 0x00000018 /* Periodic Timer A period shift */ 293*4882a593Smuzhiyun #define MAMR_PTAE 0x00800000 /* Periodic Timer A Enable */ 294*4882a593Smuzhiyun #define MAMR_AMA_MSK 0x00700000 /* Addess Multiplexing size A */ 295*4882a593Smuzhiyun #define MAMR_AMA_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */ 296*4882a593Smuzhiyun #define MAMR_AMA_TYPE_1 0x00100000 /* Addess Multiplexing Type 1 */ 297*4882a593Smuzhiyun #define MAMR_AMA_TYPE_2 0x00200000 /* Addess Multiplexing Type 2 */ 298*4882a593Smuzhiyun #define MAMR_AMA_TYPE_3 0x00300000 /* Addess Multiplexing Type 3 */ 299*4882a593Smuzhiyun #define MAMR_AMA_TYPE_4 0x00400000 /* Addess Multiplexing Type 4 */ 300*4882a593Smuzhiyun #define MAMR_AMA_TYPE_5 0x00500000 /* Addess Multiplexing Type 5 */ 301*4882a593Smuzhiyun #define MAMR_DSA_MSK 0x00060000 /* Disable Timer period mask */ 302*4882a593Smuzhiyun #define MAMR_DSA_1_CYCL 0x00000000 /* 1 cycle Disable Period */ 303*4882a593Smuzhiyun #define MAMR_DSA_2_CYCL 0x00020000 /* 2 cycle Disable Period */ 304*4882a593Smuzhiyun #define MAMR_DSA_3_CYCL 0x00040000 /* 3 cycle Disable Period */ 305*4882a593Smuzhiyun #define MAMR_DSA_4_CYCL 0x00060000 /* 4 cycle Disable Period */ 306*4882a593Smuzhiyun #define MAMR_G0CLA_MSK 0x0000E000 /* General Line 0 Control A */ 307*4882a593Smuzhiyun #define MAMR_G0CLA_A12 0x00000000 /* General Line 0 : A12 */ 308*4882a593Smuzhiyun #define MAMR_G0CLA_A11 0x00002000 /* General Line 0 : A11 */ 309*4882a593Smuzhiyun #define MAMR_G0CLA_A10 0x00004000 /* General Line 0 : A10 */ 310*4882a593Smuzhiyun #define MAMR_G0CLA_A9 0x00006000 /* General Line 0 : A9 */ 311*4882a593Smuzhiyun #define MAMR_G0CLA_A8 0x00008000 /* General Line 0 : A8 */ 312*4882a593Smuzhiyun #define MAMR_G0CLA_A7 0x0000A000 /* General Line 0 : A7 */ 313*4882a593Smuzhiyun #define MAMR_G0CLA_A6 0x0000C000 /* General Line 0 : A6 */ 314*4882a593Smuzhiyun #define MAMR_G0CLA_A5 0x0000E000 /* General Line 0 : A5 */ 315*4882a593Smuzhiyun #define MAMR_GPL_A4DIS 0x00001000 /* GPL_A4 ouput line Disable */ 316*4882a593Smuzhiyun #define MAMR_RLFA_MSK 0x00000F00 /* Read Loop Field A mask */ 317*4882a593Smuzhiyun #define MAMR_RLFA_1X 0x00000100 /* The Read Loop is executed 1 time */ 318*4882a593Smuzhiyun #define MAMR_RLFA_2X 0x00000200 /* The Read Loop is executed 2 times */ 319*4882a593Smuzhiyun #define MAMR_RLFA_3X 0x00000300 /* The Read Loop is executed 3 times */ 320*4882a593Smuzhiyun #define MAMR_RLFA_4X 0x00000400 /* The Read Loop is executed 4 times */ 321*4882a593Smuzhiyun #define MAMR_RLFA_5X 0x00000500 /* The Read Loop is executed 5 times */ 322*4882a593Smuzhiyun #define MAMR_RLFA_6X 0x00000600 /* The Read Loop is executed 6 times */ 323*4882a593Smuzhiyun #define MAMR_RLFA_7X 0x00000700 /* The Read Loop is executed 7 times */ 324*4882a593Smuzhiyun #define MAMR_RLFA_8X 0x00000800 /* The Read Loop is executed 8 times */ 325*4882a593Smuzhiyun #define MAMR_RLFA_9X 0x00000900 /* The Read Loop is executed 9 times */ 326*4882a593Smuzhiyun #define MAMR_RLFA_10X 0x00000A00 /* The Read Loop is executed 10 times */ 327*4882a593Smuzhiyun #define MAMR_RLFA_11X 0x00000B00 /* The Read Loop is executed 11 times */ 328*4882a593Smuzhiyun #define MAMR_RLFA_12X 0x00000C00 /* The Read Loop is executed 12 times */ 329*4882a593Smuzhiyun #define MAMR_RLFA_13X 0x00000D00 /* The Read Loop is executed 13 times */ 330*4882a593Smuzhiyun #define MAMR_RLFA_14X 0x00000E00 /* The Read Loop is executed 14 times */ 331*4882a593Smuzhiyun #define MAMR_RLFA_15X 0x00000F00 /* The Read Loop is executed 15 times */ 332*4882a593Smuzhiyun #define MAMR_RLFA_16X 0x00000000 /* The Read Loop is executed 16 times */ 333*4882a593Smuzhiyun #define MAMR_WLFA_MSK 0x000000F0 /* Write Loop Field A mask */ 334*4882a593Smuzhiyun #define MAMR_WLFA_1X 0x00000010 /* The Write Loop is executed 1 time */ 335*4882a593Smuzhiyun #define MAMR_WLFA_2X 0x00000020 /* The Write Loop is executed 2 times */ 336*4882a593Smuzhiyun #define MAMR_WLFA_3X 0x00000030 /* The Write Loop is executed 3 times */ 337*4882a593Smuzhiyun #define MAMR_WLFA_4X 0x00000040 /* The Write Loop is executed 4 times */ 338*4882a593Smuzhiyun #define MAMR_WLFA_5X 0x00000050 /* The Write Loop is executed 5 times */ 339*4882a593Smuzhiyun #define MAMR_WLFA_6X 0x00000060 /* The Write Loop is executed 6 times */ 340*4882a593Smuzhiyun #define MAMR_WLFA_7X 0x00000070 /* The Write Loop is executed 7 times */ 341*4882a593Smuzhiyun #define MAMR_WLFA_8X 0x00000080 /* The Write Loop is executed 8 times */ 342*4882a593Smuzhiyun #define MAMR_WLFA_9X 0x00000090 /* The Write Loop is executed 9 times */ 343*4882a593Smuzhiyun #define MAMR_WLFA_10X 0x000000A0 /* The Write Loop is executed 10 times */ 344*4882a593Smuzhiyun #define MAMR_WLFA_11X 0x000000B0 /* The Write Loop is executed 11 times */ 345*4882a593Smuzhiyun #define MAMR_WLFA_12X 0x000000C0 /* The Write Loop is executed 12 times */ 346*4882a593Smuzhiyun #define MAMR_WLFA_13X 0x000000D0 /* The Write Loop is executed 13 times */ 347*4882a593Smuzhiyun #define MAMR_WLFA_14X 0x000000E0 /* The Write Loop is executed 14 times */ 348*4882a593Smuzhiyun #define MAMR_WLFA_15X 0x000000F0 /* The Write Loop is executed 15 times */ 349*4882a593Smuzhiyun #define MAMR_WLFA_16X 0x00000000 /* The Write Loop is executed 16 times */ 350*4882a593Smuzhiyun #define MAMR_TLFA_MSK 0x0000000F /* Timer Loop Field A mask */ 351*4882a593Smuzhiyun #define MAMR_TLFA_1X 0x00000001 /* The Timer Loop is executed 1 time */ 352*4882a593Smuzhiyun #define MAMR_TLFA_2X 0x00000002 /* The Timer Loop is executed 2 times */ 353*4882a593Smuzhiyun #define MAMR_TLFA_3X 0x00000003 /* The Timer Loop is executed 3 times */ 354*4882a593Smuzhiyun #define MAMR_TLFA_4X 0x00000004 /* The Timer Loop is executed 4 times */ 355*4882a593Smuzhiyun #define MAMR_TLFA_5X 0x00000005 /* The Timer Loop is executed 5 times */ 356*4882a593Smuzhiyun #define MAMR_TLFA_6X 0x00000006 /* The Timer Loop is executed 6 times */ 357*4882a593Smuzhiyun #define MAMR_TLFA_7X 0x00000007 /* The Timer Loop is executed 7 times */ 358*4882a593Smuzhiyun #define MAMR_TLFA_8X 0x00000008 /* The Timer Loop is executed 8 times */ 359*4882a593Smuzhiyun #define MAMR_TLFA_9X 0x00000009 /* The Timer Loop is executed 9 times */ 360*4882a593Smuzhiyun #define MAMR_TLFA_10X 0x0000000A /* The Timer Loop is executed 10 times */ 361*4882a593Smuzhiyun #define MAMR_TLFA_11X 0x0000000B /* The Timer Loop is executed 11 times */ 362*4882a593Smuzhiyun #define MAMR_TLFA_12X 0x0000000C /* The Timer Loop is executed 12 times */ 363*4882a593Smuzhiyun #define MAMR_TLFA_13X 0x0000000D /* The Timer Loop is executed 13 times */ 364*4882a593Smuzhiyun #define MAMR_TLFA_14X 0x0000000E /* The Timer Loop is executed 14 times */ 365*4882a593Smuzhiyun #define MAMR_TLFA_15X 0x0000000F /* The Timer Loop is executed 15 times */ 366*4882a593Smuzhiyun #define MAMR_TLFA_16X 0x00000000 /* The Timer Loop is executed 16 times */ 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun /*----------------------------------------------------------------------- 369*4882a593Smuzhiyun * Machine B Mode Register 16-13 370*4882a593Smuzhiyun */ 371*4882a593Smuzhiyun #define MBMR_PTB_MSK 0xFF000000 /* Periodic Timer B period mask */ 372*4882a593Smuzhiyun #define MBMR_PTB_SHIFT 0x00000018 /* Periodic Timer B period shift */ 373*4882a593Smuzhiyun #define MBMR_PTBE 0x00800000 /* Periodic Timer B Enable */ 374*4882a593Smuzhiyun #define MBMR_AMB_MSK 0x00700000 /* Addess Multiplex size B */ 375*4882a593Smuzhiyun #define MBMR_AMB_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */ 376*4882a593Smuzhiyun #define MBMR_AMB_TYPE_1 0x00100000 /* Addess Multiplexing Type 1 */ 377*4882a593Smuzhiyun #define MBMR_AMB_TYPE_2 0x00200000 /* Addess Multiplexing Type 2 */ 378*4882a593Smuzhiyun #define MBMR_AMB_TYPE_3 0x00300000 /* Addess Multiplexing Type 3 */ 379*4882a593Smuzhiyun #define MBMR_AMB_TYPE_4 0x00400000 /* Addess Multiplexing Type 4 */ 380*4882a593Smuzhiyun #define MBMR_AMB_TYPE_5 0x00500000 /* Addess Multiplexing Type 5 */ 381*4882a593Smuzhiyun #define MBMR_DSB_MSK 0x00060000 /* Disable Timer period mask */ 382*4882a593Smuzhiyun #define MBMR_DSB_1_CYCL 0x00000000 /* 1 cycle Disable Period */ 383*4882a593Smuzhiyun #define MBMR_DSB_2_CYCL 0x00020000 /* 2 cycle Disable Period */ 384*4882a593Smuzhiyun #define MBMR_DSB_3_CYCL 0x00040000 /* 3 cycle Disable Period */ 385*4882a593Smuzhiyun #define MBMR_DSB_4_CYCL 0x00060000 /* 4 cycle Disable Period */ 386*4882a593Smuzhiyun #define MBMR_G0CLB_MSK 0x0000E000 /* General Line 0 Control B */ 387*4882a593Smuzhiyun #define MBMR_G0CLB_A12 0x00000000 /* General Line 0 : A12 */ 388*4882a593Smuzhiyun #define MBMR_G0CLB_A11 0x00002000 /* General Line 0 : A11 */ 389*4882a593Smuzhiyun #define MBMR_G0CLB_A10 0x00004000 /* General Line 0 : A10 */ 390*4882a593Smuzhiyun #define MBMR_G0CLB_A9 0x00006000 /* General Line 0 : A9 */ 391*4882a593Smuzhiyun #define MBMR_G0CLB_A8 0x00008000 /* General Line 0 : A8 */ 392*4882a593Smuzhiyun #define MBMR_G0CLB_A7 0x0000A000 /* General Line 0 : A7 */ 393*4882a593Smuzhiyun #define MBMR_G0CLB_A6 0x0000C000 /* General Line 0 : A6 */ 394*4882a593Smuzhiyun #define MBMR_G0CLB_A5 0x0000E000 /* General Line 0 : A5 */ 395*4882a593Smuzhiyun #define MBMR_GPL_B4DIS 0x00001000 /* GPL_B4 ouput line Disable */ 396*4882a593Smuzhiyun #define MBMR_RLFB_MSK 0x00000F00 /* Read Loop Field B mask */ 397*4882a593Smuzhiyun #define MBMR_RLFB_1X 0x00000100 /* The Read Loop is executed 1 time */ 398*4882a593Smuzhiyun #define MBMR_RLFB_2X 0x00000200 /* The Read Loop is executed 2 times */ 399*4882a593Smuzhiyun #define MBMR_RLFB_3X 0x00000300 /* The Read Loop is executed 3 times */ 400*4882a593Smuzhiyun #define MBMR_RLFB_4X 0x00000400 /* The Read Loop is executed 4 times */ 401*4882a593Smuzhiyun #define MBMR_RLFB_5X 0x00000500 /* The Read Loop is executed 5 times */ 402*4882a593Smuzhiyun #define MBMR_RLFB_6X 0x00000600 /* The Read Loop is executed 6 times */ 403*4882a593Smuzhiyun #define MBMR_RLFB_7X 0x00000700 /* The Read Loop is executed 7 times */ 404*4882a593Smuzhiyun #define MBMR_RLFB_8X 0x00000800 /* The Read Loop is executed 8 times */ 405*4882a593Smuzhiyun #define MBMR_RLFB_9X 0x00000900 /* The Read Loop is executed 9 times */ 406*4882a593Smuzhiyun #define MBMR_RLFB_10X 0x00000A00 /* The Read Loop is executed 10 times */ 407*4882a593Smuzhiyun #define MBMR_RLFB_11X 0x00000B00 /* The Read Loop is executed 11 times */ 408*4882a593Smuzhiyun #define MBMR_RLFB_12X 0x00000C00 /* The Read Loop is executed 12 times */ 409*4882a593Smuzhiyun #define MBMR_RLFB_13X 0x00000D00 /* The Read Loop is executed 13 times */ 410*4882a593Smuzhiyun #define MBMR_RLFB_14X 0x00000E00 /* The Read Loop is executed 14 times */ 411*4882a593Smuzhiyun #define MBMR_RLFB_15X 0x00000f00 /* The Read Loop is executed 15 times */ 412*4882a593Smuzhiyun #define MBMR_RLFB_16X 0x00000000 /* The Read Loop is executed 16 times */ 413*4882a593Smuzhiyun #define MBMR_WLFB_MSK 0x000000F0 /* Write Loop Field B mask */ 414*4882a593Smuzhiyun #define MBMR_WLFB_1X 0x00000010 /* The Write Loop is executed 1 time */ 415*4882a593Smuzhiyun #define MBMR_WLFB_2X 0x00000020 /* The Write Loop is executed 2 times */ 416*4882a593Smuzhiyun #define MBMR_WLFB_3X 0x00000030 /* The Write Loop is executed 3 times */ 417*4882a593Smuzhiyun #define MBMR_WLFB_4X 0x00000040 /* The Write Loop is executed 4 times */ 418*4882a593Smuzhiyun #define MBMR_WLFB_5X 0x00000050 /* The Write Loop is executed 5 times */ 419*4882a593Smuzhiyun #define MBMR_WLFB_6X 0x00000060 /* The Write Loop is executed 6 times */ 420*4882a593Smuzhiyun #define MBMR_WLFB_7X 0x00000070 /* The Write Loop is executed 7 times */ 421*4882a593Smuzhiyun #define MBMR_WLFB_8X 0x00000080 /* The Write Loop is executed 8 times */ 422*4882a593Smuzhiyun #define MBMR_WLFB_9X 0x00000090 /* The Write Loop is executed 9 times */ 423*4882a593Smuzhiyun #define MBMR_WLFB_10X 0x000000A0 /* The Write Loop is executed 10 times */ 424*4882a593Smuzhiyun #define MBMR_WLFB_11X 0x000000B0 /* The Write Loop is executed 11 times */ 425*4882a593Smuzhiyun #define MBMR_WLFB_12X 0x000000C0 /* The Write Loop is executed 12 times */ 426*4882a593Smuzhiyun #define MBMR_WLFB_13X 0x000000D0 /* The Write Loop is executed 13 times */ 427*4882a593Smuzhiyun #define MBMR_WLFB_14X 0x000000E0 /* The Write Loop is executed 14 times */ 428*4882a593Smuzhiyun #define MBMR_WLFB_15X 0x000000F0 /* The Write Loop is executed 15 times */ 429*4882a593Smuzhiyun #define MBMR_WLFB_16X 0x00000000 /* The Write Loop is executed 16 times */ 430*4882a593Smuzhiyun #define MBMR_TLFB_MSK 0x0000000F /* Timer Loop Field B mask */ 431*4882a593Smuzhiyun #define MBMR_TLFB_1X 0x00000001 /* The Timer Loop is executed 1 time */ 432*4882a593Smuzhiyun #define MBMR_TLFB_2X 0x00000002 /* The Timer Loop is executed 2 times */ 433*4882a593Smuzhiyun #define MBMR_TLFB_3X 0x00000003 /* The Timer Loop is executed 3 times */ 434*4882a593Smuzhiyun #define MBMR_TLFB_4X 0x00000004 /* The Timer Loop is executed 4 times */ 435*4882a593Smuzhiyun #define MBMR_TLFB_5X 0x00000005 /* The Timer Loop is executed 5 times */ 436*4882a593Smuzhiyun #define MBMR_TLFB_6X 0x00000006 /* The Timer Loop is executed 6 times */ 437*4882a593Smuzhiyun #define MBMR_TLFB_7X 0x00000007 /* The Timer Loop is executed 7 times */ 438*4882a593Smuzhiyun #define MBMR_TLFB_8X 0x00000008 /* The Timer Loop is executed 8 times */ 439*4882a593Smuzhiyun #define MBMR_TLFB_9X 0x00000009 /* The Timer Loop is executed 9 times */ 440*4882a593Smuzhiyun #define MBMR_TLFB_10X 0x0000000A /* The Timer Loop is executed 10 times */ 441*4882a593Smuzhiyun #define MBMR_TLFB_11X 0x0000000B /* The Timer Loop is executed 11 times */ 442*4882a593Smuzhiyun #define MBMR_TLFB_12X 0x0000000C /* The Timer Loop is executed 12 times */ 443*4882a593Smuzhiyun #define MBMR_TLFB_13X 0x0000000D /* The Timer Loop is executed 13 times */ 444*4882a593Smuzhiyun #define MBMR_TLFB_14X 0x0000000E /* The Timer Loop is executed 14 times */ 445*4882a593Smuzhiyun #define MBMR_TLFB_15X 0x0000000F /* The Timer Loop is executed 15 times */ 446*4882a593Smuzhiyun #define MBMR_TLFB_16X 0x00000000 /* The Timer Loop is executed 16 times */ 447*4882a593Smuzhiyun 448*4882a593Smuzhiyun /*----------------------------------------------------------------------- 449*4882a593Smuzhiyun * Timer Global Configuration Register 18-8 450*4882a593Smuzhiyun */ 451*4882a593Smuzhiyun #define TGCR_CAS4 0x8000 /* Cascade Timer 3 and 4 */ 452*4882a593Smuzhiyun #define TGCR_FRZ4 0x4000 /* Freeze timer 4 */ 453*4882a593Smuzhiyun #define TGCR_STP4 0x2000 /* Stop timer 4 */ 454*4882a593Smuzhiyun #define TGCR_RST4 0x1000 /* Reset timer 4 */ 455*4882a593Smuzhiyun #define TGCR_GM2 0x0800 /* Gate Mode for Pin 2 */ 456*4882a593Smuzhiyun #define TGCR_FRZ3 0x0400 /* Freeze timer 3 */ 457*4882a593Smuzhiyun #define TGCR_STP3 0x0200 /* Stop timer 3 */ 458*4882a593Smuzhiyun #define TGCR_RST3 0x0100 /* Reset timer 3 */ 459*4882a593Smuzhiyun #define TGCR_CAS2 0x0080 /* Cascade Timer 1 and 2 */ 460*4882a593Smuzhiyun #define TGCR_FRZ2 0x0040 /* Freeze timer 2 */ 461*4882a593Smuzhiyun #define TGCR_STP2 0x0020 /* Stop timer 2 */ 462*4882a593Smuzhiyun #define TGCR_RST2 0x0010 /* Reset timer 2 */ 463*4882a593Smuzhiyun #define TGCR_GM1 0x0008 /* Gate Mode for Pin 1 */ 464*4882a593Smuzhiyun #define TGCR_FRZ1 0x0004 /* Freeze timer 1 */ 465*4882a593Smuzhiyun #define TGCR_STP1 0x0002 /* Stop timer 1 */ 466*4882a593Smuzhiyun #define TGCR_RST1 0x0001 /* Reset timer 1 */ 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun 469*4882a593Smuzhiyun /*----------------------------------------------------------------------- 470*4882a593Smuzhiyun * Timer Mode Register 18-9 471*4882a593Smuzhiyun */ 472*4882a593Smuzhiyun #define TMR_PS_MSK 0xFF00 /* Prescaler Value */ 473*4882a593Smuzhiyun #define TMR_PS_SHIFT 8 /* Prescaler position */ 474*4882a593Smuzhiyun #define TMR_CE_MSK 0x00C0 /* Capture Edge and Enable Interrupt */ 475*4882a593Smuzhiyun #define TMR_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event */ 476*4882a593Smuzhiyun #define TMR_CE_RISING 0x0040 /* Capture on Rising TINx edge only */ 477*4882a593Smuzhiyun #define TMR_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */ 478*4882a593Smuzhiyun #define TMR_CE_ANY 0x00C0 /* Capture on any TINx edge */ 479*4882a593Smuzhiyun #define TMR_OM 0x0020 /* Output Mode */ 480*4882a593Smuzhiyun #define TMR_ORI 0x0010 /* Output Reference Interrupt Enable */ 481*4882a593Smuzhiyun #define TMR_FRR 0x0008 /* Free Run/Restart */ 482*4882a593Smuzhiyun #define TMR_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */ 483*4882a593Smuzhiyun #define TMR_ICLK_IN_CAS 0x0000 /* Internally cascaded input */ 484*4882a593Smuzhiyun #define TMR_ICLK_IN_GEN 0x0002 /* Internal General system clock */ 485*4882a593Smuzhiyun #define TMR_ICLK_IN_GEN_DIV16 0x0004 /* Internal General system clk div 16 */ 486*4882a593Smuzhiyun #define TMR_ICLK_TIN_PIN 0x0006 /* TINx pin */ 487*4882a593Smuzhiyun #define TMR_GE 0x0001 /* Gate Enable */ 488*4882a593Smuzhiyun 489*4882a593Smuzhiyun 490*4882a593Smuzhiyun /*----------------------------------------------------------------------- 491*4882a593Smuzhiyun * I2C Controller Registers 492*4882a593Smuzhiyun */ 493*4882a593Smuzhiyun #define I2MOD_REVD 0x20 /* Reverese Data */ 494*4882a593Smuzhiyun #define I2MOD_GCD 0x10 /* General Call Disable */ 495*4882a593Smuzhiyun #define I2MOD_FLT 0x08 /* Clock Filter */ 496*4882a593Smuzhiyun #define I2MOD_PDIV32 0x00 /* Pre-Divider 32 */ 497*4882a593Smuzhiyun #define I2MOD_PDIV16 0x02 /* Pre-Divider 16 */ 498*4882a593Smuzhiyun #define I2MOD_PDIV8 0x04 /* Pre-Divider 8 */ 499*4882a593Smuzhiyun #define I2MOD_PDIV4 0x06 /* Pre-Divider 4 */ 500*4882a593Smuzhiyun #define I2MOD_EN 0x01 /* Enable */ 501*4882a593Smuzhiyun 502*4882a593Smuzhiyun #define I2CER_TXE 0x10 /* Tx Error */ 503*4882a593Smuzhiyun #define I2CER_BSY 0x04 /* Busy Condition */ 504*4882a593Smuzhiyun #define I2CER_TXB 0x02 /* Tx Buffer Transmitted */ 505*4882a593Smuzhiyun #define I2CER_RXB 0x01 /* Rx Buffer Received */ 506*4882a593Smuzhiyun #define I2CER_ALL (I2CER_TXE | I2CER_BSY | I2CER_TXB | I2CER_RXB) 507*4882a593Smuzhiyun 508*4882a593Smuzhiyun #define I2COM_STR 0x80 /* Start Transmit */ 509*4882a593Smuzhiyun #define I2COM_MASTER 0x01 /* Master mode */ 510*4882a593Smuzhiyun 511*4882a593Smuzhiyun /*----------------------------------------------------------------------- 512*4882a593Smuzhiyun * SPI Controller Registers 31-10 513*4882a593Smuzhiyun */ 514*4882a593Smuzhiyun #define SPI_EMASK 0x37 /* Event Mask */ 515*4882a593Smuzhiyun #define SPI_MME 0x20 /* Multi-Master Error */ 516*4882a593Smuzhiyun #define SPI_TXE 0x10 /* Transmit Error */ 517*4882a593Smuzhiyun #define SPI_BSY 0x04 /* Busy */ 518*4882a593Smuzhiyun #define SPI_TXB 0x02 /* Tx Buffer Empty */ 519*4882a593Smuzhiyun #define SPI_RXB 0x01 /* RX Buffer full/closed */ 520*4882a593Smuzhiyun 521*4882a593Smuzhiyun #define SPI_STR 0x80 /* SPCOM: Start transmit */ 522*4882a593Smuzhiyun 523*4882a593Smuzhiyun /*----------------------------------------------------------------------- 524*4882a593Smuzhiyun * PCMCIA Interface General Control Register 17-12 525*4882a593Smuzhiyun */ 526*4882a593Smuzhiyun #define PCMCIA_GCRX_CXRESET 0x00000040 527*4882a593Smuzhiyun #define PCMCIA_GCRX_CXOE 0x00000080 528*4882a593Smuzhiyun 529*4882a593Smuzhiyun #define PCMCIA_VS1(slot) (0x80000000 >> (slot << 4)) 530*4882a593Smuzhiyun #define PCMCIA_VS2(slot) (0x40000000 >> (slot << 4)) 531*4882a593Smuzhiyun #define PCMCIA_VS_MASK(slot) (0xC0000000 >> (slot << 4)) 532*4882a593Smuzhiyun #define PCMCIA_VS_SHIFT(slot) (30 - (slot << 4)) 533*4882a593Smuzhiyun 534*4882a593Smuzhiyun #define PCMCIA_WP(slot) (0x20000000 >> (slot << 4)) 535*4882a593Smuzhiyun #define PCMCIA_CD2(slot) (0x10000000 >> (slot << 4)) 536*4882a593Smuzhiyun #define PCMCIA_CD1(slot) (0x08000000 >> (slot << 4)) 537*4882a593Smuzhiyun #define PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4)) 538*4882a593Smuzhiyun #define PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4)) 539*4882a593Smuzhiyun #define PCMCIA_RDY(slot) (0x01000000 >> (slot << 4)) 540*4882a593Smuzhiyun #define PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4)) 541*4882a593Smuzhiyun #define PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4)) 542*4882a593Smuzhiyun #define PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4)) 543*4882a593Smuzhiyun #define PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4)) 544*4882a593Smuzhiyun #define PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4)) 545*4882a593Smuzhiyun 546*4882a593Smuzhiyun /*----------------------------------------------------------------------- 547*4882a593Smuzhiyun * PCMCIA Option Register Definitions 548*4882a593Smuzhiyun * 549*4882a593Smuzhiyun * Bank Sizes: 550*4882a593Smuzhiyun */ 551*4882a593Smuzhiyun #define PCMCIA_BSIZE_1 0x00000000 /* Bank size: 1 Bytes */ 552*4882a593Smuzhiyun #define PCMCIA_BSIZE_2 0x08000000 /* Bank size: 2 Bytes */ 553*4882a593Smuzhiyun #define PCMCIA_BSIZE_4 0x18000000 /* Bank size: 4 Bytes */ 554*4882a593Smuzhiyun #define PCMCIA_BSIZE_8 0x10000000 /* Bank size: 8 Bytes */ 555*4882a593Smuzhiyun #define PCMCIA_BSIZE_16 0x30000000 /* Bank size: 16 Bytes */ 556*4882a593Smuzhiyun #define PCMCIA_BSIZE_32 0x38000000 /* Bank size: 32 Bytes */ 557*4882a593Smuzhiyun #define PCMCIA_BSIZE_64 0x28000000 /* Bank size: 64 Bytes */ 558*4882a593Smuzhiyun #define PCMCIA_BSIZE_128 0x20000000 /* Bank size: 128 Bytes */ 559*4882a593Smuzhiyun #define PCMCIA_BSIZE_256 0x60000000 /* Bank size: 256 Bytes */ 560*4882a593Smuzhiyun #define PCMCIA_BSIZE_512 0x68000000 /* Bank size: 512 Bytes */ 561*4882a593Smuzhiyun #define PCMCIA_BSIZE_1K 0x78000000 /* Bank size: 1 kB */ 562*4882a593Smuzhiyun #define PCMCIA_BSIZE_2K 0x70000000 /* Bank size: 2 kB */ 563*4882a593Smuzhiyun #define PCMCIA_BSIZE_4K 0x50000000 /* Bank size: 4 kB */ 564*4882a593Smuzhiyun #define PCMCIA_BSIZE_8K 0x58000000 /* Bank size: 8 kB */ 565*4882a593Smuzhiyun #define PCMCIA_BSIZE_16K 0x48000000 /* Bank size: 16 kB */ 566*4882a593Smuzhiyun #define PCMCIA_BSIZE_32K 0x40000000 /* Bank size: 32 kB */ 567*4882a593Smuzhiyun #define PCMCIA_BSIZE_64K 0xC0000000 /* Bank size: 64 kB */ 568*4882a593Smuzhiyun #define PCMCIA_BSIZE_128K 0xC8000000 /* Bank size: 128 kB */ 569*4882a593Smuzhiyun #define PCMCIA_BSIZE_256K 0xD8000000 /* Bank size: 256 kB */ 570*4882a593Smuzhiyun #define PCMCIA_BSIZE_512K 0xD0000000 /* Bank size: 512 kB */ 571*4882a593Smuzhiyun #define PCMCIA_BSIZE_1M 0xF0000000 /* Bank size: 1 MB */ 572*4882a593Smuzhiyun #define PCMCIA_BSIZE_2M 0xF8000000 /* Bank size: 2 MB */ 573*4882a593Smuzhiyun #define PCMCIA_BSIZE_4M 0xE8000000 /* Bank size: 4 MB */ 574*4882a593Smuzhiyun #define PCMCIA_BSIZE_8M 0xE0000000 /* Bank size: 8 MB */ 575*4882a593Smuzhiyun #define PCMCIA_BSIZE_16M 0xA0000000 /* Bank size: 16 MB */ 576*4882a593Smuzhiyun #define PCMCIA_BSIZE_32M 0xA8000000 /* Bank size: 32 MB */ 577*4882a593Smuzhiyun #define PCMCIA_BSIZE_64M 0xB8000000 /* Bank size: 64 MB */ 578*4882a593Smuzhiyun 579*4882a593Smuzhiyun /* PCMCIA Timing */ 580*4882a593Smuzhiyun #define PCMCIA_SHT(t) ((t & 0x0F)<<16) /* Strobe Hold Time */ 581*4882a593Smuzhiyun #define PCMCIA_SST(t) ((t & 0x0F)<<12) /* Strobe Setup Time */ 582*4882a593Smuzhiyun #define PCMCIA_SL(t) ((t==32) ? 0 : ((t & 0x1F)<<7)) /* Strobe Length */ 583*4882a593Smuzhiyun 584*4882a593Smuzhiyun /* PCMCIA Port Sizes */ 585*4882a593Smuzhiyun #define PCMCIA_PPS_8 0x00000000 /* 8 bit port size */ 586*4882a593Smuzhiyun #define PCMCIA_PPS_16 0x00000040 /* 16 bit port size */ 587*4882a593Smuzhiyun 588*4882a593Smuzhiyun /* PCMCIA Region Select */ 589*4882a593Smuzhiyun #define PCMCIA_PRS_MEM 0x00000000 /* Common Memory Space */ 590*4882a593Smuzhiyun #define PCMCIA_PRS_ATTR 0x00000010 /* Attribute Space */ 591*4882a593Smuzhiyun #define PCMCIA_PRS_IO 0x00000018 /* I/O Space */ 592*4882a593Smuzhiyun #define PCMCIA_PRS_DMA 0x00000020 /* DMA, normal transfer */ 593*4882a593Smuzhiyun #define PCMCIA_PRS_DMA_LAST 0x00000028 /* DMA, last transactn */ 594*4882a593Smuzhiyun #define PCMCIA_PRS_CEx 0x00000030 /* A[22:23] ==> CE1,CE2 */ 595*4882a593Smuzhiyun 596*4882a593Smuzhiyun #define PCMCIA_PSLOT_A 0x00000000 /* Slot A */ 597*4882a593Smuzhiyun #define PCMCIA_PSLOT_B 0x00000004 /* Slot B */ 598*4882a593Smuzhiyun #define PCMCIA_WPROT 0x00000002 /* Write Protect */ 599*4882a593Smuzhiyun #define PCMCIA_PV 0x00000001 /* Valid Bit */ 600*4882a593Smuzhiyun 601*4882a593Smuzhiyun #define UPMA 0x00000000 602*4882a593Smuzhiyun #define UPMB 0x00800000 603*4882a593Smuzhiyun 604*4882a593Smuzhiyun #endif /* __MPCXX_H__ */ 605