1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2006 Freescale Semiconductor. 3*4882a593Smuzhiyun * Jeffrey Brown 4*4882a593Smuzhiyun * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __MPC86xx_H__ 8*4882a593Smuzhiyun #define __MPC86xx_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <asm/fsl_lbc.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */ 13*4882a593Smuzhiyun #define _START_OFFSET EXC_OFF_SYS_RESET 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * platform register addresses 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define GUTS_SVR (CONFIG_SYS_CCSRBAR + 0xE00A4) 20*4882a593Smuzhiyun #define MCM_ABCR (CONFIG_SYS_CCSRBAR + 0x01000) 21*4882a593Smuzhiyun #define MCM_DBCR (CONFIG_SYS_CCSRBAR + 0x01008) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* 24*4882a593Smuzhiyun * l2cr values. Look in config_<BOARD>.h for the actual setup 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun #define l2cr 1017 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define L2CR_L2E 0x80000000 /* bit 0 - enable */ 29*4882a593Smuzhiyun #define L2CR_L2PE 0x40000000 /* bit 1 - data parity */ 30*4882a593Smuzhiyun #define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */ 31*4882a593Smuzhiyun #define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */ 32*4882a593Smuzhiyun #define L2CR_L2DO 0x00010000 /* bit 15 - data-only mode */ 33*4882a593Smuzhiyun #define L2CR_REP 0x00001000 /* bit 19 - l2 replacement alg */ 34*4882a593Smuzhiyun #define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */ 35*4882a593Smuzhiyun #define L2CR_L2IP 0x00000001 /* global invalidate in progress */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define HID0_XBSEN 0x00000100 38*4882a593Smuzhiyun #define HID0_HIGH_BAT_EN 0x00800000 39*4882a593Smuzhiyun #define HID0_XAEN 0x00020000 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun typedef struct { 44*4882a593Smuzhiyun unsigned long freq_processor; 45*4882a593Smuzhiyun unsigned long freq_systembus; 46*4882a593Smuzhiyun unsigned long freq_localbus; 47*4882a593Smuzhiyun } MPC86xx_SYS_INFO; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define l1icache_enable icache_enable 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun void l2cache_enable(void); 52*4882a593Smuzhiyun void l1dcache_enable(void); 53*4882a593Smuzhiyun get_hid0(void)54*4882a593Smuzhiyunstatic __inline__ unsigned long get_hid0 (void) 55*4882a593Smuzhiyun { 56*4882a593Smuzhiyun unsigned long hid0; 57*4882a593Smuzhiyun asm volatile("mfspr %0, 1008" : "=r" (hid0) :); 58*4882a593Smuzhiyun return hid0; 59*4882a593Smuzhiyun } 60*4882a593Smuzhiyun get_hid1(void)61*4882a593Smuzhiyunstatic __inline__ unsigned long get_hid1 (void) 62*4882a593Smuzhiyun { 63*4882a593Smuzhiyun unsigned long hid1; 64*4882a593Smuzhiyun asm volatile("mfspr %0, 1009" : "=r" (hid1) :); 65*4882a593Smuzhiyun return hid1; 66*4882a593Smuzhiyun } 67*4882a593Smuzhiyun set_hid0(unsigned long hid0)68*4882a593Smuzhiyunstatic __inline__ void set_hid0 (unsigned long hid0) 69*4882a593Smuzhiyun { 70*4882a593Smuzhiyun asm volatile("mtspr 1008, %0" : : "r" (hid0)); 71*4882a593Smuzhiyun } 72*4882a593Smuzhiyun set_hid1(unsigned long hid1)73*4882a593Smuzhiyunstatic __inline__ void set_hid1 (unsigned long hid1) 74*4882a593Smuzhiyun { 75*4882a593Smuzhiyun asm volatile("mtspr 1009, %0" : : "r" (hid1)); 76*4882a593Smuzhiyun } 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun get_l2cr(void)79*4882a593Smuzhiyunstatic __inline__ unsigned long get_l2cr (void) 80*4882a593Smuzhiyun { 81*4882a593Smuzhiyun unsigned long l2cr_val; 82*4882a593Smuzhiyun asm volatile("mfspr %0, 1017" : "=r" (l2cr_val) :); 83*4882a593Smuzhiyun return l2cr_val; 84*4882a593Smuzhiyun } 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun void setup_ddr_bat(phys_addr_t dram_size); 87*4882a593Smuzhiyun extern void setup_bats(void); 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #endif /* _ASMLANGUAGE */ 90*4882a593Smuzhiyun #endif /* __MPC86xx_H__ */ 91