1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2004, 2007 Freescale Semiconductor. 3*4882a593Smuzhiyun * Copyright(c) 2003 Motorola Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __MPC85xx_H__ 7*4882a593Smuzhiyun #define __MPC85xx_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #if defined(CONFIG_E500) 10*4882a593Smuzhiyun #include <e500.h> 11*4882a593Smuzhiyun #endif 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * SCCR - System Clock Control Register, 9-8 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun #define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */ 17*4882a593Smuzhiyun #define SCCR_DFBRG_MSK 0x00000003 /* Division by BRGCLK Mask */ 18*4882a593Smuzhiyun #define SCCR_DFBRG_SHIFT 0 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */ 21*4882a593Smuzhiyun #define SCCR_DFBRG01 0x00000001 /* BRGCLK div by 16 (normal) */ 22*4882a593Smuzhiyun #define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ 23*4882a593Smuzhiyun #define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* 26*4882a593Smuzhiyun * Define default values for some CCSR macros to make header files cleaner* 27*4882a593Smuzhiyun * 28*4882a593Smuzhiyun * To completely disable CCSR relocation in a board header file, define 29*4882a593Smuzhiyun * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS 30*4882a593Smuzhiyun * to a value that is the same as CONFIG_SYS_CCSRBAR. 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #ifdef CONFIG_SYS_CCSRBAR_PHYS 34*4882a593Smuzhiyun #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \ 35*4882a593Smuzhiyun CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." 36*4882a593Smuzhiyun #endif 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE 39*4882a593Smuzhiyun #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH 40*4882a593Smuzhiyun #undef CONFIG_SYS_CCSRBAR_PHYS_LOW 41*4882a593Smuzhiyun #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 42*4882a593Smuzhiyun #endif 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #ifndef CONFIG_SYS_CCSRBAR 45*4882a593Smuzhiyun #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 46*4882a593Smuzhiyun #endif 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH 49*4882a593Smuzhiyun #ifdef CONFIG_PHYS_64BIT 50*4882a593Smuzhiyun #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf 51*4882a593Smuzhiyun #else 52*4882a593Smuzhiyun #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 53*4882a593Smuzhiyun #endif 54*4882a593Smuzhiyun #endif 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW 57*4882a593Smuzhiyun #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 58*4882a593Smuzhiyun #endif 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ 61*4882a593Smuzhiyun CONFIG_SYS_CCSRBAR_PHYS_LOW) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #ifndef CONFIG_SYS_IMMR 64*4882a593Smuzhiyun #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 65*4882a593Smuzhiyun #endif 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #endif /* __MPC85xx_H__ */ 68