1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> 3*4882a593Smuzhiyun * Andreas Heppel <aheppel@sysgo.de> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _MPC106_PCI_H 9*4882a593Smuzhiyun #define _MPC106_PCI_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Defines for the MPC106 PCI Config address and data registers followed by 13*4882a593Smuzhiyun * defines for the standard PCI device configuration header. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #define PCIDEVID_MPC106 0x0 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * MPC106 Registers 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun #define MPC106_REG 0x80000000 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #ifdef CONFIG_SYS_ADDRESS_MAP_A 23*4882a593Smuzhiyun #define MPC106_REG_ADDR 0x80000cf8 24*4882a593Smuzhiyun #define MPC106_REG_DATA 0x80000cfc 25*4882a593Smuzhiyun #define MPC106_ISA_IO_PHYS 0x80000000 26*4882a593Smuzhiyun #define MPC106_ISA_IO_BUS 0x00000000 27*4882a593Smuzhiyun #define MPC106_ISA_IO_SIZE 0x00800000 28*4882a593Smuzhiyun #define MPC106_PCI_IO_PHYS 0x81000000 29*4882a593Smuzhiyun #define MPC106_PCI_IO_BUS 0x01000000 30*4882a593Smuzhiyun #define MPC106_PCI_IO_SIZE 0x3e800000 31*4882a593Smuzhiyun #define MPC106_PCI_MEM_PHYS 0xc0000000 32*4882a593Smuzhiyun #define MPC106_PCI_MEM_BUS 0x00000000 33*4882a593Smuzhiyun #define MPC106_PCI_MEM_SIZE 0x3f000000 34*4882a593Smuzhiyun #define MPC106_PCI_MEMORY_PHYS 0x00000000 35*4882a593Smuzhiyun #define MPC106_PCI_MEMORY_BUS 0x80000000 36*4882a593Smuzhiyun #define MPC106_PCI_MEMORY_SIZE 0x80000000 37*4882a593Smuzhiyun #else 38*4882a593Smuzhiyun #define MPC106_REG_ADDR 0xfec00cf8 39*4882a593Smuzhiyun #define MPC106_REG_DATA 0xfee00cfc 40*4882a593Smuzhiyun #define MPC106_ISA_MEM_PHYS 0xfd000000 41*4882a593Smuzhiyun #define MPC106_ISA_MEM_BUS 0x00000000 42*4882a593Smuzhiyun #define MPC106_ISA_MEM_SIZE 0x01000000 43*4882a593Smuzhiyun #define MPC106_ISA_IO_PHYS 0xfe000000 44*4882a593Smuzhiyun #define MPC106_ISA_IO_BUS 0x00000000 45*4882a593Smuzhiyun #define MPC106_ISA_IO_SIZE 0x00800000 46*4882a593Smuzhiyun #define MPC106_PCI_IO_PHYS 0xfe800000 47*4882a593Smuzhiyun #define MPC106_PCI_IO_BUS 0x00800000 48*4882a593Smuzhiyun #define MPC106_PCI_IO_SIZE 0x00400000 49*4882a593Smuzhiyun #define MPC106_PCI_MEM_PHYS 0x80000000 50*4882a593Smuzhiyun #define MPC106_PCI_MEM_BUS 0x80000000 51*4882a593Smuzhiyun #define MPC106_PCI_MEM_SIZE 0x7d000000 52*4882a593Smuzhiyun #define MPC106_PCI_MEMORY_PHYS 0x00000000 53*4882a593Smuzhiyun #define MPC106_PCI_MEMORY_BUS 0x00000000 54*4882a593Smuzhiyun #define MPC106_PCI_MEMORY_SIZE 0x40000000 55*4882a593Smuzhiyun #endif 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define CMD_SERR 0x0100 58*4882a593Smuzhiyun #define PCI_CMD_MASTER 0x0004 59*4882a593Smuzhiyun #define PCI_CMD_MEMEN 0x0002 60*4882a593Smuzhiyun #define PCI_CMD_IOEN 0x0001 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define PCI_STAT_NO_RSV_BITS 0xffff 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define PCI_BUSNUM 0x40 65*4882a593Smuzhiyun #define PCI_SUBBUSNUM 0x41 66*4882a593Smuzhiyun #define PCI_DISCOUNT 0x42 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define PCI_PICR1 0xA8 69*4882a593Smuzhiyun #define PICR1_CF_CBA(value) ((value & 0xff) << 24) 70*4882a593Smuzhiyun #define PICR1_CF_BREAD_WS(value) ((value & 0x3) << 22) 71*4882a593Smuzhiyun #define PICR1_PROC_TYPE_603 0x40000 72*4882a593Smuzhiyun #define PICR1_PROC_TYPE_604 0x60000 73*4882a593Smuzhiyun #define PICR1_MCP_EN 0x800 74*4882a593Smuzhiyun #define PICR1_CF_DPARK 0x200 75*4882a593Smuzhiyun #define PICR1_CF_LOOP_SNOOP 0x10 76*4882a593Smuzhiyun #define PICR1_CF_L2_COPY_BACK 0x2 77*4882a593Smuzhiyun #define PICR1_CF_L2_CACHE_MASK 0x3 78*4882a593Smuzhiyun #define PICR1_CF_APARK 0x8 79*4882a593Smuzhiyun #define PICR1_ADDRESS_MAP 0x10000 80*4882a593Smuzhiyun #define PICR1_XIO_MODE 0x80000 81*4882a593Smuzhiyun #define PICR1_CF_CACHE_1G 0x200000 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define PCI_PICR2 0xAC 84*4882a593Smuzhiyun #define PICR2_CF_SNOOP_WS(value) ((value & 0x3) << 18) 85*4882a593Smuzhiyun #define PICR2_CF_FLUSH_L2 0x10000000 86*4882a593Smuzhiyun #define PICR2_CF_L2_HIT_DELAY(value) ((value & 0x3) << 9) 87*4882a593Smuzhiyun #define PICR2_CF_APHASE_WS(value) ((value & 0x3) << 2) 88*4882a593Smuzhiyun #define PICR2_CF_INV_MODE 0x00001000 89*4882a593Smuzhiyun #define PICR2_CF_MOD_HIGH 0x00020000 90*4882a593Smuzhiyun #define PICR2_CF_HIT_HIGH 0x00010000 91*4882a593Smuzhiyun #define PICR2_L2_SIZE_256K 0x00000000 92*4882a593Smuzhiyun #define PICR2_L2_SIZE_512K 0x00000010 93*4882a593Smuzhiyun #define PICR2_L2_SIZE_1MB 0x00000020 94*4882a593Smuzhiyun #define PICR2_L2_EN 0x40000000 95*4882a593Smuzhiyun #define PICR2_L2_UPDATE_EN 0x80000000 96*4882a593Smuzhiyun #define PICR2_CF_ADDR_ONLY_DISABLE 0x00004000 97*4882a593Smuzhiyun #define PICR2_CF_FAST_CASTOUT 0x00000080 98*4882a593Smuzhiyun #define PICR2_CF_WDATA 0x00000001 99*4882a593Smuzhiyun #define PICR2_CF_DATA_RAM_PBURST 0x00400000 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* 102*4882a593Smuzhiyun * Memory controller 103*4882a593Smuzhiyun */ 104*4882a593Smuzhiyun #define MPC106_MCCR1 0xF0 105*4882a593Smuzhiyun #define MCCR1_TYPE_EDO 0x00020000 106*4882a593Smuzhiyun #define MCCR1_BK0_9BITS 0x0 107*4882a593Smuzhiyun #define MCCR1_BK0_10BITS 0x1 108*4882a593Smuzhiyun #define MCCR1_BK0_11BITS 0x2 109*4882a593Smuzhiyun #define MCCR1_BK0_12BITS 0x3 110*4882a593Smuzhiyun #define MCCR1_BK1_9BITS 0x0 111*4882a593Smuzhiyun #define MCCR1_BK1_10BITS 0x4 112*4882a593Smuzhiyun #define MCCR1_BK1_11BITS 0x8 113*4882a593Smuzhiyun #define MCCR1_BK1_12BITS 0xC 114*4882a593Smuzhiyun #define MCCR1_BK2_9BITS 0x00 115*4882a593Smuzhiyun #define MCCR1_BK2_10BITS 0x10 116*4882a593Smuzhiyun #define MCCR1_BK2_11BITS 0x20 117*4882a593Smuzhiyun #define MCCR1_BK2_12BITS 0x30 118*4882a593Smuzhiyun #define MCCR1_BK3_9BITS 0x00 119*4882a593Smuzhiyun #define MCCR1_BK3_10BITS 0x40 120*4882a593Smuzhiyun #define MCCR1_BK3_11BITS 0x80 121*4882a593Smuzhiyun #define MCCR1_BK3_12BITS 0xC0 122*4882a593Smuzhiyun #define MCCR1_MEMGO 0x00080000 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #define MPC106_MCCR2 0xF4 125*4882a593Smuzhiyun #define MPC106_MCCR3 0xF8 126*4882a593Smuzhiyun #define MPC106_MCCR4 0xFC 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #define MPC106_MSAR1 0x80 129*4882a593Smuzhiyun #define MPC106_EMSAR1 0x88 130*4882a593Smuzhiyun #define MPC106_EMSAR2 0x8C 131*4882a593Smuzhiyun #define MPC106_MEAR1 0x90 132*4882a593Smuzhiyun #define MPC106_EMEAR1 0x98 133*4882a593Smuzhiyun #define MPC106_EMEAR2 0x9C 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define MPC106_MBER 0xA0 136*4882a593Smuzhiyun #define MBER_BANK0 0x1 137*4882a593Smuzhiyun #define MBER_BANK1 0x2 138*4882a593Smuzhiyun #define MBER_BANK2 0x4 139*4882a593Smuzhiyun #define MBER_BANK3 0x8 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #endif 142