1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2009 Marc Kleine-Budde <mkl@pengutronix.de> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ASM_ARCH_MC9SDZ60_H 10*4882a593Smuzhiyun #define __ASM_ARCH_MC9SDZ60_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /** 13*4882a593Smuzhiyun * Register addresses for the MC9SDZ60 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * @note: these match those in the kernel drivers/mxc/mcu_pmic/mc9s08dz60.h 16*4882a593Smuzhiyun * but not include/linux/mfd/mc9s08dz60/pmic.h 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun enum mc9sdz60_reg { 20*4882a593Smuzhiyun MC9SDZ60_REG_VERSION = 0x00, 21*4882a593Smuzhiyun /* reserved 0x01 */ 22*4882a593Smuzhiyun MC9SDZ60_REG_SECS = 0x02, 23*4882a593Smuzhiyun MC9SDZ60_REG_MINS = 0x03, 24*4882a593Smuzhiyun MC9SDZ60_REG_HRS = 0x04, 25*4882a593Smuzhiyun MC9SDZ60_REG_DAY = 0x05, 26*4882a593Smuzhiyun MC9SDZ60_REG_DATE = 0x06, 27*4882a593Smuzhiyun MC9SDZ60_REG_MONTH = 0x07, 28*4882a593Smuzhiyun MC9SDZ60_REG_YEAR = 0x08, 29*4882a593Smuzhiyun MC9SDZ60_REG_ALARM_SECS = 0x09, 30*4882a593Smuzhiyun MC9SDZ60_REG_ALARM_MINS = 0x0a, 31*4882a593Smuzhiyun MC9SDZ60_REG_ALARM_HRS = 0x0b, 32*4882a593Smuzhiyun /* reserved 0x0c */ 33*4882a593Smuzhiyun /* reserved 0x0d */ 34*4882a593Smuzhiyun MC9SDZ60_REG_TS_CONTROL = 0x0e, 35*4882a593Smuzhiyun MC9SDZ60_REG_X_LOW = 0x0f, 36*4882a593Smuzhiyun MC9SDZ60_REG_Y_LOW = 0x10, 37*4882a593Smuzhiyun MC9SDZ60_REG_XY_HIGH = 0x11, 38*4882a593Smuzhiyun MC9SDZ60_REG_X_LEFT_LOW = 0x12, 39*4882a593Smuzhiyun MC9SDZ60_REG_X_LEFT_HIGH = 0x13, 40*4882a593Smuzhiyun MC9SDZ60_REG_X_RIGHT = 0x14, 41*4882a593Smuzhiyun MC9SDZ60_REG_Y_TOP_LOW = 0x15, 42*4882a593Smuzhiyun MC9SDZ60_REG_Y_TOP_HIGH = 0x16, 43*4882a593Smuzhiyun MC9SDZ60_REG_Y_BOTTOM = 0x17, 44*4882a593Smuzhiyun /* reserved 0x18 */ 45*4882a593Smuzhiyun /* reserved 0x19 */ 46*4882a593Smuzhiyun MC9SDZ60_REG_RESET_1 = 0x1a, 47*4882a593Smuzhiyun MC9SDZ60_REG_RESET_2 = 0x1b, 48*4882a593Smuzhiyun MC9SDZ60_REG_POWER_CTL = 0x1c, 49*4882a593Smuzhiyun MC9SDZ60_REG_DELAY_CONFIG = 0x1d, 50*4882a593Smuzhiyun /* reserved 0x1e */ 51*4882a593Smuzhiyun /* reserved 0x1f */ 52*4882a593Smuzhiyun MC9SDZ60_REG_GPIO_1 = 0x20, 53*4882a593Smuzhiyun MC9SDZ60_REG_GPIO_2 = 0x21, 54*4882a593Smuzhiyun MC9SDZ60_REG_KPD_1 = 0x22, 55*4882a593Smuzhiyun MC9SDZ60_REG_KPD_2 = 0x23, 56*4882a593Smuzhiyun MC9SDZ60_REG_KPD_CONTROL = 0x24, 57*4882a593Smuzhiyun MC9SDZ60_REG_INT_ENABLE_1 = 0x25, 58*4882a593Smuzhiyun MC9SDZ60_REG_INT_ENABLE_2 = 0x26, 59*4882a593Smuzhiyun MC9SDZ60_REG_INT_FLAG_1 = 0x27, 60*4882a593Smuzhiyun MC9SDZ60_REG_INT_FLAG_2 = 0x28, 61*4882a593Smuzhiyun MC9SDZ60_REG_DES_FLAG = 0x29, 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun extern u8 mc9sdz60_reg_read(enum mc9sdz60_reg reg); 65*4882a593Smuzhiyun extern void mc9sdz60_reg_write(enum mc9sdz60_reg reg, u8 val); 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #endif /* __ASM_ARCH_MC9SDZ60_H */ 68