1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2012 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __MC34704_H__ 8*4882a593Smuzhiyun #define __MC34704_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun enum { 11*4882a593Smuzhiyun MC34704_RESERVED0_REG = 0, /* 0x00 */ 12*4882a593Smuzhiyun MC34704_GENERAL1_REG, /* 0x01 */ 13*4882a593Smuzhiyun MC34704_GENERAL2_REG, /* 0x02 */ 14*4882a593Smuzhiyun MC34704_GENERAL3_REG, /* 0x03 */ 15*4882a593Smuzhiyun MC34704_RESERVED4_REG, /* 0x04 */ 16*4882a593Smuzhiyun MC34704_VGSET2_REG, /* 0x05 */ 17*4882a593Smuzhiyun MC34704_REG2SET1_REG, /* 0x06 */ 18*4882a593Smuzhiyun MC34704_REG2SET2_REG, /* 0x07 */ 19*4882a593Smuzhiyun MC34704_REG3SET1_REG, /* 0x08 */ 20*4882a593Smuzhiyun MC34704_REG3SET2_REG, /* 0x09 */ 21*4882a593Smuzhiyun MC34704_REG4SET1_REG, /* 0x0a */ 22*4882a593Smuzhiyun MC34704_REG4SET2_REG, /* 0x0b */ 23*4882a593Smuzhiyun MC34704_REG5SET1_REG, /* 0x0c */ 24*4882a593Smuzhiyun MC34704_REG5SET2_REG, /* 0x0d */ 25*4882a593Smuzhiyun MC34704_REG5SET3_REG, /* 0x0e */ 26*4882a593Smuzhiyun MC34704_RESERVEDF_REG, /* 0x0f */ 27*4882a593Smuzhiyun MC34704_RESERVED10_REG, /* 0x10 */ 28*4882a593Smuzhiyun MC34704_RESERVED11_REG, /* 0x11 */ 29*4882a593Smuzhiyun MC34704_RESERVED12_REG, /* 0x12 */ 30*4882a593Smuzhiyun MC34704_FSW2SET_REG, /* 0x13 */ 31*4882a593Smuzhiyun MC34704_RESERVED14_REG, /* 0x14 */ 32*4882a593Smuzhiyun MC34704_REG8SET1_REG, /* 0x15 */ 33*4882a593Smuzhiyun MC34704_REG8SET2_REG, /* 0x16 */ 34*4882a593Smuzhiyun MC34704_REG8SET3_REG, /* 0x17 */ 35*4882a593Smuzhiyun MC34704_FAULTS_REG, /* 0x18 */ 36*4882a593Smuzhiyun MC34704_I2CSET1, /* 0x19 */ 37*4882a593Smuzhiyun MC34704_NUM_OF_REGS, 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* GENERAL2 register fields */ 41*4882a593Smuzhiyun #define ONOFFE (1 << 0) 42*4882a593Smuzhiyun #define ONOFFD (1 << 1) 43*4882a593Smuzhiyun #define ONOFFA (1 << 3) 44*4882a593Smuzhiyun #define ALLOFF (1 << 4) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #endif /* __MC34704_H__ */ 47