xref: /OK3568_Linux_fs/u-boot/include/mc13892.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * (C) Copyright 2010
3*4882a593Smuzhiyun  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * (C) Copyright 2009 Freescale Semiconductor, Inc.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #ifndef __MC13892_H__
12*4882a593Smuzhiyun #define __MC13892_H__
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun /* REG_CHARGE */
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #define VCHRG0		(1 << 0)
17*4882a593Smuzhiyun #define VCHRG1		(1 << 1)
18*4882a593Smuzhiyun #define VCHRG2		(1 << 2)
19*4882a593Smuzhiyun #define ICHRG0		(1 << 3)
20*4882a593Smuzhiyun #define ICHRG1		(1 << 4)
21*4882a593Smuzhiyun #define ICHRG2		(1 << 5)
22*4882a593Smuzhiyun #define ICHRG3		(1 << 6)
23*4882a593Smuzhiyun #define TREN		(1 << 7)
24*4882a593Smuzhiyun #define ACKLPB		(1 << 8)
25*4882a593Smuzhiyun #define THCHKB		(1 << 9)
26*4882a593Smuzhiyun #define FETOVRD		(1 << 10)
27*4882a593Smuzhiyun #define FETCTRL		(1 << 11)
28*4882a593Smuzhiyun #define RVRSMODE	(1 << 13)
29*4882a593Smuzhiyun #define PLIM0		(1 << 15)
30*4882a593Smuzhiyun #define PLIM1		(1 << 16)
31*4882a593Smuzhiyun #define PLIMDIS		(1 << 17)
32*4882a593Smuzhiyun #define CHRGLEDEN	(1 << 18)
33*4882a593Smuzhiyun #define CHGTMRRST	(1 << 19)
34*4882a593Smuzhiyun #define CHGRESTART	(1 << 20)
35*4882a593Smuzhiyun #define CHGAUTOB	(1 << 21)
36*4882a593Smuzhiyun #define CYCLB		(1 << 22)
37*4882a593Smuzhiyun #define CHGAUTOVIB	(1 << 23)
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun /* REG_SETTING_0/1 */
40*4882a593Smuzhiyun #define VO_1_20V	0
41*4882a593Smuzhiyun #define VO_1_30V	1
42*4882a593Smuzhiyun #define VO_1_50V	2
43*4882a593Smuzhiyun #define VO_1_80V	3
44*4882a593Smuzhiyun #define VO_1_10V	4
45*4882a593Smuzhiyun #define VO_2_00V	5
46*4882a593Smuzhiyun #define VO_2_77V	6
47*4882a593Smuzhiyun #define VO_2_40V	7
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun #define VIOL		2
50*4882a593Smuzhiyun #define VDIG		4
51*4882a593Smuzhiyun #define VGEN		6
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun /* SWxMode for Normal/Standby Mode */
54*4882a593Smuzhiyun #define SWMODE_OFF_OFF		0
55*4882a593Smuzhiyun #define SWMODE_PWM_OFF		1
56*4882a593Smuzhiyun #define SWMODE_PWMPS_OFF	2
57*4882a593Smuzhiyun #define SWMODE_PFM_OFF		3
58*4882a593Smuzhiyun #define SWMODE_AUTO_OFF		4
59*4882a593Smuzhiyun #define SWMODE_PWM_PWM		5
60*4882a593Smuzhiyun #define SWMODE_PWM_AUTO		6
61*4882a593Smuzhiyun #define SWMODE_AUTO_AUTO	8
62*4882a593Smuzhiyun #define SWMODE_PWM_PWMPS	9
63*4882a593Smuzhiyun #define SWMODE_PWMS_PWMPS	10
64*4882a593Smuzhiyun #define SWMODE_PWMS_AUTO	11
65*4882a593Smuzhiyun #define SWMODE_AUTO_PFM		12
66*4882a593Smuzhiyun #define SWMODE_PWM_PFM		13
67*4882a593Smuzhiyun #define SWMODE_PWMS_PFM		14
68*4882a593Smuzhiyun #define SWMODE_PFM_PFM		15
69*4882a593Smuzhiyun #define SWMODE_MASK		0x0F
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun #define SWMODE1_SHIFT		0
72*4882a593Smuzhiyun #define SWMODE2_SHIFT		10
73*4882a593Smuzhiyun #define SWMODE3_SHIFT		0
74*4882a593Smuzhiyun #define SWMODE4_SHIFT		8
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun /* Fields in REG_SETTING_1 */
77*4882a593Smuzhiyun #define VVIDEO_2_7	(0 << 2)
78*4882a593Smuzhiyun #define VVIDEO_2_775	(1 << 2)
79*4882a593Smuzhiyun #define VVIDEO_2_5	(2 << 2)
80*4882a593Smuzhiyun #define VVIDEO_2_6	(3 << 2)
81*4882a593Smuzhiyun #define VVIDEO_MASK	(3 << 2)
82*4882a593Smuzhiyun #define VAUDIO_2_3	(0 << 4)
83*4882a593Smuzhiyun #define VAUDIO_2_5	(1 << 4)
84*4882a593Smuzhiyun #define VAUDIO_2_775	(2 << 4)
85*4882a593Smuzhiyun #define VAUDIO_3_0	(3 << 4)
86*4882a593Smuzhiyun #define VAUDIO_MASK	(3 << 4)
87*4882a593Smuzhiyun #define VSD_1_8		(0 << 6)
88*4882a593Smuzhiyun #define VSD_2_0		(1 << 6)
89*4882a593Smuzhiyun #define VSD_2_6		(2 << 6)
90*4882a593Smuzhiyun #define VSD_2_7		(3 << 6)
91*4882a593Smuzhiyun #define VSD_2_8		(4 << 6)
92*4882a593Smuzhiyun #define VSD_2_9		(5 << 6)
93*4882a593Smuzhiyun #define VSD_3_0		(6 << 6)
94*4882a593Smuzhiyun #define VSD_3_15	(7 << 6)
95*4882a593Smuzhiyun #define VSD_MASK	(7 << 6)
96*4882a593Smuzhiyun #define VGEN1_1_2	0
97*4882a593Smuzhiyun #define VGEN1_1_5	1
98*4882a593Smuzhiyun #define VGEN1_2_775	2
99*4882a593Smuzhiyun #define VGEN1_3_15	3
100*4882a593Smuzhiyun #define VGEN1_MASK	3
101*4882a593Smuzhiyun #define VGEN2_1_2	(0 << 6)
102*4882a593Smuzhiyun #define VGEN2_1_5	(1 << 6)
103*4882a593Smuzhiyun #define VGEN2_1_6	(2 << 6)
104*4882a593Smuzhiyun #define VGEN2_1_8	(3 << 6)
105*4882a593Smuzhiyun #define VGEN2_2_7	(4 << 6)
106*4882a593Smuzhiyun #define VGEN2_2_8	(5 << 6)
107*4882a593Smuzhiyun #define VGEN2_3_0	(6 << 6)
108*4882a593Smuzhiyun #define VGEN2_3_15	(7 << 6)
109*4882a593Smuzhiyun #define VGEN2_MASK	(7 << 6)
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun /* Fields in REG_SETTING_1 */
112*4882a593Smuzhiyun #define VGEN3_1_8	(0 << 14)
113*4882a593Smuzhiyun #define VGEN3_2_9	(1 << 14)
114*4882a593Smuzhiyun #define VGEN3_MASK	(1 << 14)
115*4882a593Smuzhiyun #define VDIG_1_05	(0 << 4)
116*4882a593Smuzhiyun #define VDIG_1_25	(1 << 4)
117*4882a593Smuzhiyun #define VDIG_1_65	(2 << 4)
118*4882a593Smuzhiyun #define VDIG_1_8	(3 << 4)
119*4882a593Smuzhiyun #define VDIG_MASK	(3 << 4)
120*4882a593Smuzhiyun #define VCAM_2_5	(0 << 16)
121*4882a593Smuzhiyun #define VCAM_2_6	(1 << 16)
122*4882a593Smuzhiyun #define VCAM_2_75	(2 << 16)
123*4882a593Smuzhiyun #define VCAM_3_0	(3 << 16)
124*4882a593Smuzhiyun #define VCAM_MASK	(3 << 16)
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun /* Reg Mode 0 */
127*4882a593Smuzhiyun #define VGEN1EN		(1 << 0)
128*4882a593Smuzhiyun #define VGEN1STBY	(1 << 1)
129*4882a593Smuzhiyun #define VGEN1MODE	(1 << 2)
130*4882a593Smuzhiyun #define VIOHIEN		(1 << 3)
131*4882a593Smuzhiyun #define VIOHISTBY	(1 << 4)
132*4882a593Smuzhiyun #define VDIGEN		(1 << 9)
133*4882a593Smuzhiyun #define VDIGSTBY	(1 << 10)
134*4882a593Smuzhiyun #define VGEN2EN		(1 << 12)
135*4882a593Smuzhiyun #define VGEN2STBY	(1 << 13)
136*4882a593Smuzhiyun #define VGEN2MODE	(1 << 14)
137*4882a593Smuzhiyun #define VPLLEN		(1 << 15)
138*4882a593Smuzhiyun #define VPLLSTBY	(1 << 16)
139*4882a593Smuzhiyun #define VUSBEN		(1 << 18)
140*4882a593Smuzhiyun #define VUSBSTBY	(1 << 19)
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun /* Reg Mode 1 */
143*4882a593Smuzhiyun #define VGEN3EN		(1 << 0)
144*4882a593Smuzhiyun #define VGEN3STBY	(1 << 1)
145*4882a593Smuzhiyun #define VGEN3MODE	(1 << 2)
146*4882a593Smuzhiyun #define VGEN3CONFIG	(1 << 3)
147*4882a593Smuzhiyun #define VCAMEN		(1 << 6)
148*4882a593Smuzhiyun #define VCAMSTBY	(1 << 7)
149*4882a593Smuzhiyun #define VCAMMODE	(1 << 8)
150*4882a593Smuzhiyun #define VCAMCONFIG	(1 << 9)
151*4882a593Smuzhiyun #define VVIDEOEN	(1 << 12)
152*4882a593Smuzhiyun #define VIDEOSTBY	(1 << 13)
153*4882a593Smuzhiyun #define VVIDEOMODE	(1 << 14)
154*4882a593Smuzhiyun #define VAUDIOEN	(1 << 15)
155*4882a593Smuzhiyun #define VAUDIOSTBY	(1 << 16)
156*4882a593Smuzhiyun #define VSDEN		(1 << 18)
157*4882a593Smuzhiyun #define VSDSTBY		(1 << 19)
158*4882a593Smuzhiyun #define VSDMODE		(1 << 20)
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun /* Reg Power Control 2*/
161*4882a593Smuzhiyun #define WDIRESET	(1 << 12)
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun /* SWx Output Volts */
164*4882a593Smuzhiyun #define SWX_OUT_MASK	0x1F
165*4882a593Smuzhiyun #define SWX_OUT_1_25	0x1A
166*4882a593Smuzhiyun #define SWX_OUT_1_30    0X1C
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun /* Buck Switchers (SW1,2,3,4) Output Voltage */
169*4882a593Smuzhiyun /*
170*4882a593Smuzhiyun  * NOTE: These values are for SWxHI = 0,
171*4882a593Smuzhiyun  * SWxHI = 1 adds 0.5V to the desired voltage
172*4882a593Smuzhiyun  */
173*4882a593Smuzhiyun #define SWx_0_600V	0
174*4882a593Smuzhiyun #define SWx_0_625V	1
175*4882a593Smuzhiyun #define SWx_0_650V	2
176*4882a593Smuzhiyun #define SWx_0_675V	3
177*4882a593Smuzhiyun #define SWx_0_700V	4
178*4882a593Smuzhiyun #define SWx_0_725V	5
179*4882a593Smuzhiyun #define SWx_0_750V	6
180*4882a593Smuzhiyun #define SWx_0_775V	7
181*4882a593Smuzhiyun #define SWx_0_800V	8
182*4882a593Smuzhiyun #define SWx_0_825V	9
183*4882a593Smuzhiyun #define SWx_0_850V	10
184*4882a593Smuzhiyun #define SWx_0_875V	11
185*4882a593Smuzhiyun #define SWx_0_900V	12
186*4882a593Smuzhiyun #define SWx_0_925V	13
187*4882a593Smuzhiyun #define SWx_0_950V	14
188*4882a593Smuzhiyun #define SWx_0_975V	15
189*4882a593Smuzhiyun #define SWx_1_000V	16
190*4882a593Smuzhiyun #define SWx_1_025V	17
191*4882a593Smuzhiyun #define SWx_1_050V	18
192*4882a593Smuzhiyun #define SWx_1_075V	19
193*4882a593Smuzhiyun #define SWx_1_100V	20
194*4882a593Smuzhiyun #define SWx_1_125V	21
195*4882a593Smuzhiyun #define SWx_1_150V	22
196*4882a593Smuzhiyun #define SWx_1_175V	23
197*4882a593Smuzhiyun #define SWx_1_200V	24
198*4882a593Smuzhiyun #define SWx_1_225V	25
199*4882a593Smuzhiyun #define SWx_1_250V	26
200*4882a593Smuzhiyun #define SWx_1_275V	27
201*4882a593Smuzhiyun #define SWx_1_300V	28
202*4882a593Smuzhiyun #define SWx_1_325V	29
203*4882a593Smuzhiyun #define SWx_1_350V	30
204*4882a593Smuzhiyun #define SWx_1_375V	31
205*4882a593Smuzhiyun #define SWx_VOLT_MASK	0x1F
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun #endif
208