1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2007 3*4882a593Smuzhiyun * DENX Software Engineering, Anatolij Gustschin, agust@denx.de 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* 9*4882a593Smuzhiyun * mb862xx.h - Graphic interface for Fujitsu CoralP/Lime 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef _MB862XX_H_ 13*4882a593Smuzhiyun #define _MB862XX_H_ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define PCI_VENDOR_ID_FUJITSU 0x10CF 16*4882a593Smuzhiyun #define PCI_DEVICE_ID_CORAL_P 0x2019 17*4882a593Smuzhiyun #define PCI_DEVICE_ID_CORAL_PA 0x201E 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define MB862XX_TYPE_LIME 0x1 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define GC_HOST_BASE 0x01fc0000 22*4882a593Smuzhiyun #define GC_DISP_BASE 0x01fd0000 23*4882a593Smuzhiyun #define GC_DRAW_BASE 0x01ff0000 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Host interface registers */ 26*4882a593Smuzhiyun #define GC_SRST 0x0000002c 27*4882a593Smuzhiyun #define GC_CCF 0x00000038 28*4882a593Smuzhiyun #define GC_CID 0x000000f0 29*4882a593Smuzhiyun #define GC_MMR 0x0000fffc 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * Display Controller registers 33*4882a593Smuzhiyun * _A means the offset is aligned, we use these for boards 34*4882a593Smuzhiyun * with 8-/16-bit GDC access not working or buggy. 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun #define GC_DCM0 0x00000000 37*4882a593Smuzhiyun #define GC_HTP_A 0x00000004 38*4882a593Smuzhiyun #define GC_HTP 0x00000006 39*4882a593Smuzhiyun #define GC_HDB_HDP_A 0x00000008 40*4882a593Smuzhiyun #define GC_HDP 0x00000008 41*4882a593Smuzhiyun #define GC_HDB 0x0000000a 42*4882a593Smuzhiyun #define GC_VSW_HSW_HSP_A 0x0000000c 43*4882a593Smuzhiyun #define GC_HSP 0x0000000c 44*4882a593Smuzhiyun #define GC_HSW 0x0000000e 45*4882a593Smuzhiyun #define GC_VSW 0x0000000f 46*4882a593Smuzhiyun #define GC_VTR_A 0x00000010 47*4882a593Smuzhiyun #define GC_VTR 0x00000012 48*4882a593Smuzhiyun #define GC_VDP_VSP_A 0x00000014 49*4882a593Smuzhiyun #define GC_VSP 0x00000014 50*4882a593Smuzhiyun #define GC_VDP 0x00000016 51*4882a593Smuzhiyun #define GC_WY_WX 0x00000018 52*4882a593Smuzhiyun #define GC_WH_WW 0x0000001c 53*4882a593Smuzhiyun #define GC_L0M 0x00000020 54*4882a593Smuzhiyun #define GC_L0OA0 0x00000024 55*4882a593Smuzhiyun #define GC_L0DA0 0x00000028 56*4882a593Smuzhiyun #define GC_L0DY_L0DX 0x0000002c 57*4882a593Smuzhiyun #define GC_L2M 0x00000040 58*4882a593Smuzhiyun #define GC_L2OA0 0x00000044 59*4882a593Smuzhiyun #define GC_L2DA0 0x00000048 60*4882a593Smuzhiyun #define GC_L2OA1 0x0000004c 61*4882a593Smuzhiyun #define GC_L2DA1 0x00000050 62*4882a593Smuzhiyun #define GC_L2DX 0x00000054 63*4882a593Smuzhiyun #define GC_L2DY 0x00000056 64*4882a593Smuzhiyun #define GC_DCM1 0x00000100 65*4882a593Smuzhiyun #define GC_DCM2 0x00000104 66*4882a593Smuzhiyun #define GC_DCM3 0x00000108 67*4882a593Smuzhiyun #define GC_L0EM 0x00000110 68*4882a593Smuzhiyun #define GC_L0WY_L0WX 0x00000114 69*4882a593Smuzhiyun #define GC_L0WH_L0WW 0x00000118 70*4882a593Smuzhiyun #define GC_L2EM 0x00000130 71*4882a593Smuzhiyun #define GC_L2WX 0x00000134 72*4882a593Smuzhiyun #define GC_L2WY 0x00000136 73*4882a593Smuzhiyun #define GC_L2WW 0x00000138 74*4882a593Smuzhiyun #define GC_L2WH 0x0000013a 75*4882a593Smuzhiyun #define GC_L0PAL0 0x00000400 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* Drawing registers */ 78*4882a593Smuzhiyun #define GC_CTR 0x00000400 79*4882a593Smuzhiyun #define GC_IFCNT 0x00000408 80*4882a593Smuzhiyun #define GC_FBR 0x00000440 81*4882a593Smuzhiyun #define GC_XRES 0x00000444 82*4882a593Smuzhiyun #define GC_CXMIN 0x00000454 83*4882a593Smuzhiyun #define GC_CXMAX 0x00000458 84*4882a593Smuzhiyun #define GC_CYMIN 0x0000045c 85*4882a593Smuzhiyun #define GC_CYMAX 0x00000460 86*4882a593Smuzhiyun #define GC_FC 0x00000480 87*4882a593Smuzhiyun #define GC_BC 0x00000484 88*4882a593Smuzhiyun #define GC_FIFO 0x000004a0 89*4882a593Smuzhiyun #define GC_REV 0x00008084 90*4882a593Smuzhiyun #define GC_GEO_FIFO 0x00008400 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun typedef struct { 93*4882a593Smuzhiyun unsigned int index; 94*4882a593Smuzhiyun unsigned int value; 95*4882a593Smuzhiyun } gdc_regs; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun int mb862xx_probe(unsigned int addr); 98*4882a593Smuzhiyun const gdc_regs *board_get_regs (void); 99*4882a593Smuzhiyun unsigned int board_video_init (void); 100*4882a593Smuzhiyun void board_backlight_switch(int); 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #endif /* _MB862XX_H_ */ 103