1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * (C) Copyright 2022 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _MAX96755F_H_ 7 #define _MAX96755F_H_ 8 9 #include <linux/bitfield.h> 10 #include <asm-generic/gpio.h> 11 #include <drm_modes.h> 12 13 #define GPIO_A_REG(gpio) (0x02be + ((gpio) * 3)) 14 #define GPIO_B_REG(gpio) (0x02bf + ((gpio) * 3)) 15 #define GPIO_C_REG(gpio) (0x02c0 + ((gpio) * 3)) 16 17 /* 0000h */ 18 #define DEV_ADDR GENMASK(7, 1) 19 #define CFG_BLOCK BIT(0) 20 21 /* 0001h */ 22 #define IIC_2_EN BIT(7) 23 #define IIC_1_EN BIT(6) 24 #define DIS_REM_CC BIT(4) 25 #define TX_RATE GENMASK(3, 2) 26 27 /* 0002h */ 28 #define VID_TX_EN_U BIT(7) 29 #define VID_TX_EN_Z BIT(6) 30 #define VID_TX_EN_Y BIT(5) 31 #define VID_TX_EN_X BIT(4) 32 #define AUD_TX_EN_Y BIT(3) 33 #define AUD_TX_EN_X BIT(2) 34 35 /* 0003h */ 36 #define UART_2_EN BIT(5) 37 #define UART_1_EN BIT(4) 38 39 /* 0005h */ 40 #define LOCK_EN BIT(7) 41 #define ERRB_EN BIT(6) 42 #define PU_LF3 BIT(3) 43 #define PU_LF2 BIT(2) 44 #define PU_LF1 BIT(1) 45 #define PU_LF0 BIT(0) 46 47 /* 0006h */ 48 #define RCLKEN BIT(5) 49 50 /* 0010h */ 51 #define RESET_ALL BIT(7) 52 #define RESET_LINK BIT(6) 53 #define RESET_ONESHOT BIT(5) 54 #define AUTO_LINK BIT(4) 55 #define SLEEP BIT(3) 56 #define REG_ENABLE BIT(2) 57 #define LINK_CFG GENMASK(1, 0) 58 59 /* 0013h */ 60 #define LINK_MODE GENMASK(5, 4) 61 #define LOCKED BIT(3) 62 63 /* 0048h */ 64 #define REM_MS_EN BIT(5) 65 #define LOC_MS_EN BIT(4) 66 67 /* 0053h */ 68 #define TX_SPLIT_MASK_B BIT(5) 69 #define TX_SPLIT_MASK_A BIT(4) 70 #define TX_STR_SEL GENMASK(1, 0) 71 72 /* 0140h */ 73 #define AUD_RX_EN BIT(0) 74 75 /* 0170h */ 76 #define SPI_EN BIT(0) 77 78 /* 02beh */ 79 #define RES_CFG BIT(7) 80 #define TX_PRIO BIT(6) 81 #define TX_COMP_EN BIT(5) 82 #define GPIO_OUT BIT(4) 83 #define GPIO_IN BIT(3) 84 #define GPIO_RX_EN BIT(2) 85 #define GPIO_TX_EN BIT(1) 86 #define GPIO_OUT_DIS BIT(0) 87 88 /* 02bfh */ 89 #define PULL_UPDN_SEL GENMASK(7, 6) 90 #define OUT_TYPE BIT(5) 91 #define GPIO_TX_ID GENMASK(4, 0) 92 93 /* 02c0h */ 94 #define OVR_RES_CFG BIT(7) 95 #define GPIO_RX_ID GENMASK(4, 0) 96 97 /* 0311h */ 98 #define START_PORTBU BIT(7) 99 #define START_PORTBZ BIT(6) 100 #define START_PORTBY BIT(5) 101 #define START_PORTBX BIT(4) 102 #define START_PORTAU BIT(3) 103 #define START_PORTAZ BIT(2) 104 #define START_PORTAY BIT(1) 105 #define START_PORTAX BIT(0) 106 107 /* 032ah */ 108 #define DV_LOCK BIT(7) 109 #define DV_SWP_AB BIT(6) 110 #define LINE_ALT BIT(5) 111 #define DV_CONV BIT(2) 112 #define DV_SPL BIT(1) 113 #define DV_EN BIT(0) 114 115 /* 0330h */ 116 #define PHY_CONFIG GENMASK(2, 0) 117 #define MIPI_RX_RESET BIT(3) 118 119 /* 0331h */ 120 #define NUM_LANES GENMASK(1, 0) 121 122 /* 0385h */ 123 #define DPI_HSYNC_WIDTH_L GENMASK(7, 0) 124 125 /* 0386h */ 126 #define DPI_VYSNC_WIDTH_L GENMASK(7, 0) 127 128 /* 0387h */ 129 #define DPI_HSYNC_WIDTH_H GENMASK(3, 0) 130 #define DPI_VSYNC_WIDTH_H GENMASK(7, 4) 131 132 /* 03a4h */ 133 #define DPI_DE_SKEW_SEL BIT(1) 134 #define DPI_DESKEW_EN BIT(0) 135 136 /* 03a5h */ 137 #define DPI_VFP_L GENMASK(7, 0) 138 139 /* 03a6h */ 140 #define DPI_VFP_H GENMASK(3, 0) 141 #define DPI_VBP_L GENMASK(7, 4) 142 143 /* 03a7h */ 144 #define DPI_VBP_H GENMASK(7, 0) 145 146 /* 03a8h */ 147 #define DPI_VACT_L GENMASK(7, 0) 148 149 /* 03a9h */ 150 #define DPI_VACT_H GENMASK(3, 0) 151 152 /* 03aah */ 153 #define DPI_HFP_L GENMASK(7, 0) 154 155 /* 03abh */ 156 #define DPI_HFP_H GENMASK(3, 0) 157 #define DPI_HBP_L GENMASK(7, 4) 158 159 /* 03ach */ 160 #define DPI_HBP_H GENMASK(7, 0) 161 162 /* 03adh */ 163 #define DPI_HACT_L GENMASK(7, 0) 164 165 /* 03aeh */ 166 #define DPI_HACT_H GENMASK(4, 0) 167 168 enum link_mode { 169 DUAL_LINK, 170 LINKA, 171 LINKB, 172 SPLITTER_MODE, 173 }; 174 175 struct max96755f_priv { 176 struct udevice *dev; 177 struct gpio_desc enable_gpio; 178 bool split_mode; 179 bool dv_swp_ab; 180 bool dpi_deskew_en; 181 struct drm_display_mode mode; 182 u32 num_lanes; 183 struct gpio_desc lock_gpio; 184 u32 dsi_lane_map[4]; 185 }; 186 187 #endif 188