1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * (C) Copyright 2022 Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _MAX96745_H_ 7*4882a593Smuzhiyun #define _MAX96745_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/bitfield.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define GPIO_A_REG(gpio) (0x0200 + ((gpio) * 8)) 12*4882a593Smuzhiyun #define GPIO_B_REG(gpio) (0x0201 + ((gpio) * 8)) 13*4882a593Smuzhiyun #define GPIO_C_REG(gpio) (0x0202 + ((gpio) * 8)) 14*4882a593Smuzhiyun #define GPIO_D_REG(gpio) (0x0203 + ((gpio) * 8)) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* 0010h */ 17*4882a593Smuzhiyun #define RESET_ALL BIT(7) 18*4882a593Smuzhiyun #define SLEEP BIT(3) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* 0011h */ 21*4882a593Smuzhiyun #define CXTP_B BIT(2) 22*4882a593Smuzhiyun #define CXTP_A BIT(0) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* 0028h, 0032h */ 25*4882a593Smuzhiyun #define LINK_EN BIT(7) 26*4882a593Smuzhiyun #define TX_RATE GENMASK(3, 2) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* 0029h, 0033h */ 29*4882a593Smuzhiyun #define RESET_LINK BIT(0) 30*4882a593Smuzhiyun #define RESET_ONESHOT BIT(1) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* 002Ah, 0034h */ 33*4882a593Smuzhiyun #define LINK_LOCKED BIT(0) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 0076h, 0086h */ 36*4882a593Smuzhiyun #define DIS_REM_CC BIT(7) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* 0100h */ 39*4882a593Smuzhiyun #define VID_LINK_SEL GENMASK(2, 1) 40*4882a593Smuzhiyun #define VID_TX_EN BIT(0) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* 0200h */ 43*4882a593Smuzhiyun #define RES_CFG BIT(7) 44*4882a593Smuzhiyun #define TX_COM_EN BIT(5) 45*4882a593Smuzhiyun #define GPIO_OUT BIT(4) 46*4882a593Smuzhiyun #define GPIO_IN BIT(3) 47*4882a593Smuzhiyun #define GPIO_OUT_DIS BIT(0) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* 0201h */ 50*4882a593Smuzhiyun #define PULL_UPDN_SEL GENMASK(7, 6) 51*4882a593Smuzhiyun #define OUT_TYPEC BIT(5) 52*4882a593Smuzhiyun #define GPIO_TX_ID GENMASK(4, 0) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* 0202h */ 55*4882a593Smuzhiyun #define OVR_RES_CFG BIT(7) 56*4882a593Smuzhiyun #define IO_EDGE_RATE GENMASK(6, 5) 57*4882a593Smuzhiyun #define GPIO_RX_ID GENMASK(4, 0) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* 0203h */ 60*4882a593Smuzhiyun #define GPIO_IO_RX_EN BIT(5) 61*4882a593Smuzhiyun #define GPIO_OUT_LGC BIT(4) 62*4882a593Smuzhiyun #define GPIO_RX_EN_B BIT(3) 63*4882a593Smuzhiyun #define GPIO_TX_EN_B BIT(2) 64*4882a593Smuzhiyun #define GPIO_RX_EN_A BIT(1) 65*4882a593Smuzhiyun #define GPIO_TX_EN_A BIT(0) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #endif 68