1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2013 3*4882a593Smuzhiyun * Texas Instruments Inc, <www.ti.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Dan Murphy <dmurphy@ti.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _ASM_ARCH_XHCI_OMAP_H_ 11*4882a593Smuzhiyun #define _ASM_ARCH_XHCI_OMAP_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifdef CONFIG_DRA7XX 14*4882a593Smuzhiyun #if CONFIG_USB_XHCI_DRA7XX_INDEX == 1 15*4882a593Smuzhiyun #define OMAP_XHCI_BASE 0x488d0000 16*4882a593Smuzhiyun #define OMAP_OCP1_SCP_BASE 0x4A081000 17*4882a593Smuzhiyun #define OMAP_OTG_WRAPPER_BASE 0x488c0000 18*4882a593Smuzhiyun #elif CONFIG_USB_XHCI_DRA7XX_INDEX == 0 19*4882a593Smuzhiyun #define OMAP_XHCI_BASE 0x48890000 20*4882a593Smuzhiyun #define OMAP_OCP1_SCP_BASE 0x4A084c00 21*4882a593Smuzhiyun #define OMAP_OTG_WRAPPER_BASE 0x48880000 22*4882a593Smuzhiyun #endif /* CONFIG_USB_XHCI_DRA7XX_INDEX == 1 */ 23*4882a593Smuzhiyun #elif defined CONFIG_AM43XX 24*4882a593Smuzhiyun #define OMAP_XHCI_BASE 0x483d0000 25*4882a593Smuzhiyun #define OMAP_OCP1_SCP_BASE 0x483E8000 26*4882a593Smuzhiyun #define OMAP_OTG_WRAPPER_BASE 0x483dc100 27*4882a593Smuzhiyun #else 28*4882a593Smuzhiyun /* Default to the OMAP5 XHCI defines */ 29*4882a593Smuzhiyun #define OMAP_XHCI_BASE 0x4a030000 30*4882a593Smuzhiyun #define OMAP_OCP1_SCP_BASE 0x4a084c00 31*4882a593Smuzhiyun #define OMAP_OTG_WRAPPER_BASE 0x4A020000 32*4882a593Smuzhiyun #endif 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Phy register MACRO definitions */ 35*4882a593Smuzhiyun #define PLL_REGM_MASK 0x001FFE00 36*4882a593Smuzhiyun #define PLL_REGM_SHIFT 0x9 37*4882a593Smuzhiyun #define PLL_REGM_F_MASK 0x0003FFFF 38*4882a593Smuzhiyun #define PLL_REGM_F_SHIFT 0x0 39*4882a593Smuzhiyun #define PLL_REGN_MASK 0x000001FE 40*4882a593Smuzhiyun #define PLL_REGN_SHIFT 0x1 41*4882a593Smuzhiyun #define PLL_SELFREQDCO_MASK 0x0000000E 42*4882a593Smuzhiyun #define PLL_SELFREQDCO_SHIFT 0x1 43*4882a593Smuzhiyun #define PLL_SD_MASK 0x0003FC00 44*4882a593Smuzhiyun #define PLL_SD_SHIFT 0x9 45*4882a593Smuzhiyun #define SET_PLL_GO 0x1 46*4882a593Smuzhiyun #define PLL_TICOPWDN 0x10000 47*4882a593Smuzhiyun #define PLL_LOCK 0x2 48*4882a593Smuzhiyun #define PLL_IDLE 0x1 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 51*4882a593Smuzhiyun #define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC 52*4882a593Smuzhiyun #define USB3_PHY_PARTIAL_RX_POWERON (1 << 6) 53*4882a593Smuzhiyun #define USB3_PHY_RX_POWERON (1 << 14) 54*4882a593Smuzhiyun #define USB3_PHY_TX_POWERON (1 << 15) 55*4882a593Smuzhiyun #define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) 56*4882a593Smuzhiyun #define USB3_PWRCTL_CLK_CMD_SHIFT 14 57*4882a593Smuzhiyun #define USB3_PWRCTL_CLK_FREQ_SHIFT 22 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* USBOTGSS_WRAPPER definitions */ 60*4882a593Smuzhiyun #define USBOTGSS_WRAPRESET (1 << 17) 61*4882a593Smuzhiyun #define USBOTGSS_DMADISABLE (1 << 16) 62*4882a593Smuzhiyun #define USBOTGSS_STANDBYMODE_NO_STANDBY (1 << 4) 63*4882a593Smuzhiyun #define USBOTGSS_STANDBYMODE_SMRT (1 << 5) 64*4882a593Smuzhiyun #define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) 65*4882a593Smuzhiyun #define USBOTGSS_IDLEMODE_NOIDLE (1 << 2) 66*4882a593Smuzhiyun #define USBOTGSS_IDLEMODE_SMRT (1 << 3) 67*4882a593Smuzhiyun #define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* USBOTGSS_IRQENABLE_SET_0 bit */ 70*4882a593Smuzhiyun #define USBOTGSS_COREIRQ_EN (1 << 0) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* USBOTGSS_IRQENABLE_SET_1 bits */ 73*4882a593Smuzhiyun #define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN (1 << 0) 74*4882a593Smuzhiyun #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN (1 << 3) 75*4882a593Smuzhiyun #define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN (1 << 4) 76*4882a593Smuzhiyun #define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN (1 << 5) 77*4882a593Smuzhiyun #define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN (1 << 8) 78*4882a593Smuzhiyun #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN (1 << 11) 79*4882a593Smuzhiyun #define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN (1 << 12) 80*4882a593Smuzhiyun #define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN (1 << 13) 81*4882a593Smuzhiyun #define USBOTGSS_IRQ_SET_1_OEVT_EN (1 << 16) 82*4882a593Smuzhiyun #define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN (1 << 17) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* 85*4882a593Smuzhiyun * USBOTGSS_WRAPPER registers 86*4882a593Smuzhiyun */ 87*4882a593Smuzhiyun struct omap_dwc_wrapper { 88*4882a593Smuzhiyun u32 revision; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun u32 reserve_1[3]; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun u32 sysconfig; /* offset of 0x10 */ 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun u32 reserve_2[3]; 95*4882a593Smuzhiyun u16 reserve_3; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun u32 irqstatus_raw_0; /* offset of 0x24 */ 98*4882a593Smuzhiyun u32 irqstatus_0; 99*4882a593Smuzhiyun u32 irqenable_set_0; 100*4882a593Smuzhiyun u32 irqenable_clr_0; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun u32 irqstatus_raw_1; /* offset of 0x34 */ 103*4882a593Smuzhiyun u32 irqstatus_1; 104*4882a593Smuzhiyun u32 irqenable_set_1; 105*4882a593Smuzhiyun u32 irqenable_clr_1; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun u32 reserve_4[15]; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun u32 utmi_otg_ctrl; /* offset of 0x80 */ 110*4882a593Smuzhiyun u32 utmi_otg_status; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun u32 reserve_5[30]; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun u32 mram_offset; /* offset of 0x100 */ 115*4882a593Smuzhiyun u32 fladj; 116*4882a593Smuzhiyun u32 dbg_config; 117*4882a593Smuzhiyun u32 dbg_data; 118*4882a593Smuzhiyun u32 dev_ebc_en; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* XHCI PHY register structure */ 122*4882a593Smuzhiyun struct omap_usb3_phy { 123*4882a593Smuzhiyun u32 reserve1; 124*4882a593Smuzhiyun u32 pll_status; 125*4882a593Smuzhiyun u32 pll_go; 126*4882a593Smuzhiyun u32 pll_config_1; 127*4882a593Smuzhiyun u32 pll_config_2; 128*4882a593Smuzhiyun u32 pll_config_3; 129*4882a593Smuzhiyun u32 pll_ssc_config_1; 130*4882a593Smuzhiyun u32 pll_ssc_config_2; 131*4882a593Smuzhiyun u32 pll_config_4; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun struct omap_xhci { 135*4882a593Smuzhiyun struct omap_dwc_wrapper *otg_wrapper; 136*4882a593Smuzhiyun struct omap_usb3_phy *usb3_phy; 137*4882a593Smuzhiyun struct xhci_hccr *hcd; 138*4882a593Smuzhiyun struct dwc3 *dwc3_reg; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun /* USB PHY functions */ 142*4882a593Smuzhiyun void omap_enable_phy(struct omap_xhci *omap); 143*4882a593Smuzhiyun void omap_reset_usb_phy(struct dwc3 *dwc3_reg); 144*4882a593Smuzhiyun void usb_phy_power(int on); 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #endif /* _ASM_ARCH_XHCI_OMAP_H_ */ 147