1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2015 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * FSL USB HOST xHCI Controller 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _ASM_ARCH_XHCI_FSL_H_ 12*4882a593Smuzhiyun #define _ASM_ARCH_XHCI_FSL_H_ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Default to the FSL XHCI defines */ 15*4882a593Smuzhiyun #define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 16*4882a593Smuzhiyun #define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC 17*4882a593Smuzhiyun #define USB3_PHY_PARTIAL_RX_POWERON BIT(6) 18*4882a593Smuzhiyun #define USB3_PHY_RX_POWERON BIT(14) 19*4882a593Smuzhiyun #define USB3_PHY_TX_POWERON BIT(15) 20*4882a593Smuzhiyun #define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) 21*4882a593Smuzhiyun #define USB3_PWRCTL_CLK_CMD_SHIFT 14 22*4882a593Smuzhiyun #define USB3_PWRCTL_CLK_FREQ_SHIFT 22 23*4882a593Smuzhiyun #define USB3_ENABLE_BEAT_BURST 0xF 24*4882a593Smuzhiyun #define USB3_ENABLE_BEAT_BURST_MASK 0xFF 25*4882a593Smuzhiyun #define USB3_SET_BEAT_BURST_LIMIT 0xF00 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* USBOTGSS_WRAPPER definitions */ 28*4882a593Smuzhiyun #define USBOTGSS_WRAPRESET BIT(17) 29*4882a593Smuzhiyun #define USBOTGSS_DMADISABLE BIT(16) 30*4882a593Smuzhiyun #define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4) 31*4882a593Smuzhiyun #define USBOTGSS_STANDBYMODE_SMRT BIT(5) 32*4882a593Smuzhiyun #define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) 33*4882a593Smuzhiyun #define USBOTGSS_IDLEMODE_NOIDLE BIT(2) 34*4882a593Smuzhiyun #define USBOTGSS_IDLEMODE_SMRT BIT(3) 35*4882a593Smuzhiyun #define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* USBOTGSS_IRQENABLE_SET_0 bit */ 38*4882a593Smuzhiyun #define USBOTGSS_COREIRQ_EN BIT(1) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* USBOTGSS_IRQENABLE_SET_1 bits */ 41*4882a593Smuzhiyun #define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1) 42*4882a593Smuzhiyun #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3) 43*4882a593Smuzhiyun #define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4) 44*4882a593Smuzhiyun #define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5) 45*4882a593Smuzhiyun #define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8) 46*4882a593Smuzhiyun #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11) 47*4882a593Smuzhiyun #define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12) 48*4882a593Smuzhiyun #define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13) 49*4882a593Smuzhiyun #define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16) 50*4882a593Smuzhiyun #define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun struct fsl_xhci { 53*4882a593Smuzhiyun struct xhci_hccr *hcd; 54*4882a593Smuzhiyun struct dwc3 *dwc3_reg; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_ARCH_LS1012A) 58*4882a593Smuzhiyun #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR 59*4882a593Smuzhiyun #define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 60*4882a593Smuzhiyun #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 61*4882a593Smuzhiyun #elif defined(CONFIG_ARCH_LS2080A) 62*4882a593Smuzhiyun #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR 63*4882a593Smuzhiyun #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR 64*4882a593Smuzhiyun #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 65*4882a593Smuzhiyun #elif defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) 66*4882a593Smuzhiyun #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR 67*4882a593Smuzhiyun #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR 68*4882a593Smuzhiyun #define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_XHCI_USB3_ADDR 69*4882a593Smuzhiyun #endif 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \ 72*4882a593Smuzhiyun CONFIG_SYS_FSL_XHCI_USB2_ADDR, \ 73*4882a593Smuzhiyun CONFIG_SYS_FSL_XHCI_USB3_ADDR} 74*4882a593Smuzhiyun #endif /* _ASM_ARCH_XHCI_FSL_H_ */ 75