1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * include/linux/serial_reg.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 1992, 1994 by Theodore Ts'o. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * These are the UART port assignments, expressed as offsets from the base 9*4882a593Smuzhiyun * register. These assignments should hold for any serial port based on 10*4882a593Smuzhiyun * a 8250, 16450, or 16550(A). 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef _LINUX_SERIAL_REG_H 14*4882a593Smuzhiyun #define _LINUX_SERIAL_REG_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* 17*4882a593Smuzhiyun * DLAB=0 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun #define UART_RX 0 /* In: Receive buffer */ 20*4882a593Smuzhiyun #define UART_TX 0 /* Out: Transmit buffer */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define UART_IER 1 /* Out: Interrupt Enable Register */ 23*4882a593Smuzhiyun #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ 24*4882a593Smuzhiyun #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ 25*4882a593Smuzhiyun #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ 26*4882a593Smuzhiyun #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ 27*4882a593Smuzhiyun /* 28*4882a593Smuzhiyun * Sleep mode for ST16650 and TI16750. For the ST16650, EFR[4]=1 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun #define UART_IERX_SLEEP 0x10 /* Enable sleep mode */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define UART_IIR 2 /* In: Interrupt ID Register */ 33*4882a593Smuzhiyun #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ 34*4882a593Smuzhiyun #define UART_IIR_ID 0x0e /* Mask for the interrupt ID */ 35*4882a593Smuzhiyun #define UART_IIR_MSI 0x00 /* Modem status interrupt */ 36*4882a593Smuzhiyun #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ 37*4882a593Smuzhiyun #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ 38*4882a593Smuzhiyun #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define UART_IIR_BUSY 0x07 /* DesignWare APB Busy Detect */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define UART_IIR_RX_TIMEOUT 0x0c /* OMAP RX Timeout interrupt */ 43*4882a593Smuzhiyun #define UART_IIR_XOFF 0x10 /* OMAP XOFF/Special Character */ 44*4882a593Smuzhiyun #define UART_IIR_CTS_RTS_DSR 0x20 /* OMAP CTS/RTS/DSR Change */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define UART_FCR 2 /* Out: FIFO Control Register */ 47*4882a593Smuzhiyun #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ 48*4882a593Smuzhiyun #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ 49*4882a593Smuzhiyun #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ 50*4882a593Smuzhiyun #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * Note: The FIFO trigger levels are chip specific: 53*4882a593Smuzhiyun * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11 54*4882a593Smuzhiyun * PC16550D: 1 4 8 14 xx xx xx xx 55*4882a593Smuzhiyun * TI16C550A: 1 4 8 14 xx xx xx xx 56*4882a593Smuzhiyun * TI16C550C: 1 4 8 14 xx xx xx xx 57*4882a593Smuzhiyun * ST16C550: 1 4 8 14 xx xx xx xx 58*4882a593Smuzhiyun * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2 59*4882a593Smuzhiyun * NS16C552: 1 4 8 14 xx xx xx xx 60*4882a593Smuzhiyun * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654 61*4882a593Smuzhiyun * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750 62*4882a593Smuzhiyun * TI16C752: 8 16 56 60 8 16 32 56 63*4882a593Smuzhiyun * Tegra: 1 4 8 14 16 8 4 1 PORT_TEGRA 64*4882a593Smuzhiyun */ 65*4882a593Smuzhiyun #define UART_FCR_R_TRIG_00 0x00 66*4882a593Smuzhiyun #define UART_FCR_R_TRIG_01 0x40 67*4882a593Smuzhiyun #define UART_FCR_R_TRIG_10 0x80 68*4882a593Smuzhiyun #define UART_FCR_R_TRIG_11 0xc0 69*4882a593Smuzhiyun #define UART_FCR_T_TRIG_00 0x00 70*4882a593Smuzhiyun #define UART_FCR_T_TRIG_01 0x10 71*4882a593Smuzhiyun #define UART_FCR_T_TRIG_10 0x20 72*4882a593Smuzhiyun #define UART_FCR_T_TRIG_11 0x30 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ 75*4882a593Smuzhiyun #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ 76*4882a593Smuzhiyun #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ 77*4882a593Smuzhiyun #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ 78*4882a593Smuzhiyun #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ 79*4882a593Smuzhiyun /* 16650 definitions */ 80*4882a593Smuzhiyun #define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */ 81*4882a593Smuzhiyun #define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */ 82*4882a593Smuzhiyun #define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */ 83*4882a593Smuzhiyun #define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */ 84*4882a593Smuzhiyun #define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */ 85*4882a593Smuzhiyun #define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */ 86*4882a593Smuzhiyun #define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */ 87*4882a593Smuzhiyun #define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */ 88*4882a593Smuzhiyun #define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750) */ 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define UART_LCR 3 /* Out: Line Control Register */ 91*4882a593Smuzhiyun /* 92*4882a593Smuzhiyun * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 93*4882a593Smuzhiyun * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. 94*4882a593Smuzhiyun */ 95*4882a593Smuzhiyun #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ 96*4882a593Smuzhiyun #define UART_LCR_SBC 0x40 /* Set break control */ 97*4882a593Smuzhiyun #define UART_LCR_SPAR 0x20 /* Stick parity (?) */ 98*4882a593Smuzhiyun #define UART_LCR_EPAR 0x10 /* Even parity select */ 99*4882a593Smuzhiyun #define UART_LCR_PARITY 0x08 /* Parity Enable */ 100*4882a593Smuzhiyun #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */ 101*4882a593Smuzhiyun #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ 102*4882a593Smuzhiyun #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ 103*4882a593Smuzhiyun #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ 104*4882a593Smuzhiyun #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* 107*4882a593Smuzhiyun * Access to some registers depends on register access / configuration 108*4882a593Smuzhiyun * mode. 109*4882a593Smuzhiyun */ 110*4882a593Smuzhiyun #define UART_LCR_CONF_MODE_A UART_LCR_DLAB /* Configutation mode A */ 111*4882a593Smuzhiyun #define UART_LCR_CONF_MODE_B 0xBF /* Configutation mode B */ 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define UART_MCR 4 /* Out: Modem Control Register */ 114*4882a593Smuzhiyun #define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */ 115*4882a593Smuzhiyun #define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */ 116*4882a593Smuzhiyun #define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */ 117*4882a593Smuzhiyun #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */ 118*4882a593Smuzhiyun #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ 119*4882a593Smuzhiyun #define UART_MCR_OUT2 0x08 /* Out2 complement */ 120*4882a593Smuzhiyun #define UART_MCR_OUT1 0x04 /* Out1 complement */ 121*4882a593Smuzhiyun #define UART_MCR_RTS 0x02 /* RTS complement */ 122*4882a593Smuzhiyun #define UART_MCR_DTR 0x01 /* DTR complement */ 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #define UART_LSR 5 /* In: Line Status Register */ 125*4882a593Smuzhiyun #define UART_LSR_FIFOE 0x80 /* Fifo error */ 126*4882a593Smuzhiyun #define UART_LSR_TEMT 0x40 /* Transmitter empty */ 127*4882a593Smuzhiyun #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ 128*4882a593Smuzhiyun #define UART_LSR_BI 0x10 /* Break interrupt indicator */ 129*4882a593Smuzhiyun #define UART_LSR_FE 0x08 /* Frame error indicator */ 130*4882a593Smuzhiyun #define UART_LSR_PE 0x04 /* Parity error indicator */ 131*4882a593Smuzhiyun #define UART_LSR_OE 0x02 /* Overrun error indicator */ 132*4882a593Smuzhiyun #define UART_LSR_DR 0x01 /* Receiver data ready */ 133*4882a593Smuzhiyun #define UART_LSR_BRK_ERROR_BITS 0x1E /* BI, FE, PE, OE bits */ 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define UART_MSR 6 /* In: Modem Status Register */ 136*4882a593Smuzhiyun #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ 137*4882a593Smuzhiyun #define UART_MSR_RI 0x40 /* Ring Indicator */ 138*4882a593Smuzhiyun #define UART_MSR_DSR 0x20 /* Data Set Ready */ 139*4882a593Smuzhiyun #define UART_MSR_CTS 0x10 /* Clear to Send */ 140*4882a593Smuzhiyun #define UART_MSR_DDCD 0x08 /* Delta DCD */ 141*4882a593Smuzhiyun #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ 142*4882a593Smuzhiyun #define UART_MSR_DDSR 0x02 /* Delta DSR */ 143*4882a593Smuzhiyun #define UART_MSR_DCTS 0x01 /* Delta CTS */ 144*4882a593Smuzhiyun #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define UART_SCR 7 /* I/O: Scratch Register */ 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* 149*4882a593Smuzhiyun * DLAB=1 150*4882a593Smuzhiyun */ 151*4882a593Smuzhiyun #define UART_DLL 0 /* Out: Divisor Latch Low */ 152*4882a593Smuzhiyun #define UART_DLM 1 /* Out: Divisor Latch High */ 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* 155*4882a593Smuzhiyun * LCR=0xBF (or DLAB=1 for 16C660) 156*4882a593Smuzhiyun */ 157*4882a593Smuzhiyun #define UART_EFR 2 /* I/O: Extended Features Register */ 158*4882a593Smuzhiyun #define UART_XR_EFR 9 /* I/O: Extended Features Register (XR17D15x) */ 159*4882a593Smuzhiyun #define UART_EFR_CTS 0x80 /* CTS flow control */ 160*4882a593Smuzhiyun #define UART_EFR_RTS 0x40 /* RTS flow control */ 161*4882a593Smuzhiyun #define UART_EFR_SCD 0x20 /* Special character detect */ 162*4882a593Smuzhiyun #define UART_EFR_ECB 0x10 /* Enhanced control bit */ 163*4882a593Smuzhiyun /* 164*4882a593Smuzhiyun * the low four bits control software flow control 165*4882a593Smuzhiyun */ 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun /* 168*4882a593Smuzhiyun * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654 169*4882a593Smuzhiyun */ 170*4882a593Smuzhiyun #define UART_XON1 4 /* I/O: Xon character 1 */ 171*4882a593Smuzhiyun #define UART_XON2 5 /* I/O: Xon character 2 */ 172*4882a593Smuzhiyun #define UART_XOFF1 6 /* I/O: Xoff character 1 */ 173*4882a593Smuzhiyun #define UART_XOFF2 7 /* I/O: Xoff character 2 */ 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun /* 176*4882a593Smuzhiyun * EFR[4]=1 MCR[6]=1, TI16C752 177*4882a593Smuzhiyun */ 178*4882a593Smuzhiyun #define UART_TI752_TCR 6 /* I/O: transmission control register */ 179*4882a593Smuzhiyun #define UART_TI752_TLR 7 /* I/O: trigger level register */ 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun /* 182*4882a593Smuzhiyun * LCR=0xBF, XR16C85x 183*4882a593Smuzhiyun */ 184*4882a593Smuzhiyun #define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx 185*4882a593Smuzhiyun * In: Fifo count 186*4882a593Smuzhiyun * Out: Fifo custom trigger levels */ 187*4882a593Smuzhiyun /* 188*4882a593Smuzhiyun * These are the definitions for the Programmable Trigger Register 189*4882a593Smuzhiyun */ 190*4882a593Smuzhiyun #define UART_TRG_1 0x01 191*4882a593Smuzhiyun #define UART_TRG_4 0x04 192*4882a593Smuzhiyun #define UART_TRG_8 0x08 193*4882a593Smuzhiyun #define UART_TRG_16 0x10 194*4882a593Smuzhiyun #define UART_TRG_32 0x20 195*4882a593Smuzhiyun #define UART_TRG_64 0x40 196*4882a593Smuzhiyun #define UART_TRG_96 0x60 197*4882a593Smuzhiyun #define UART_TRG_120 0x78 198*4882a593Smuzhiyun #define UART_TRG_128 0x80 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun #define UART_FCTR 1 /* Feature Control Register */ 201*4882a593Smuzhiyun #define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */ 202*4882a593Smuzhiyun #define UART_FCTR_RTS_4DELAY 0x01 203*4882a593Smuzhiyun #define UART_FCTR_RTS_6DELAY 0x02 204*4882a593Smuzhiyun #define UART_FCTR_RTS_8DELAY 0x03 205*4882a593Smuzhiyun #define UART_FCTR_IRDA 0x04 /* IrDa data encode select */ 206*4882a593Smuzhiyun #define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */ 207*4882a593Smuzhiyun #define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */ 208*4882a593Smuzhiyun #define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */ 209*4882a593Smuzhiyun #define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */ 210*4882a593Smuzhiyun #define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */ 211*4882a593Smuzhiyun #define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */ 212*4882a593Smuzhiyun #define UART_FCTR_RX 0x00 /* Programmable trigger mode select */ 213*4882a593Smuzhiyun #define UART_FCTR_TX 0x80 /* Programmable trigger mode select */ 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun /* 216*4882a593Smuzhiyun * LCR=0xBF, FCTR[6]=1 217*4882a593Smuzhiyun */ 218*4882a593Smuzhiyun #define UART_EMSR 7 /* Extended Mode Select Register */ 219*4882a593Smuzhiyun #define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */ 220*4882a593Smuzhiyun #define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */ 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun /* 223*4882a593Smuzhiyun * The Intel XScale on-chip UARTs define these bits 224*4882a593Smuzhiyun */ 225*4882a593Smuzhiyun #define UART_IER_DMAE 0x80 /* DMA Requests Enable */ 226*4882a593Smuzhiyun #define UART_IER_UUE 0x40 /* UART Unit Enable */ 227*4882a593Smuzhiyun #define UART_IER_NRZE 0x20 /* NRZ coding Enable */ 228*4882a593Smuzhiyun #define UART_IER_RTOIE 0x10 /* Receiver Time Out Interrupt Enable */ 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun #define UART_IIR_TOD 0x08 /* Character Timeout Indication Detected */ 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun #define UART_FCR_PXAR1 0x00 /* receive FIFO threshold = 1 */ 233*4882a593Smuzhiyun #define UART_FCR_PXAR8 0x40 /* receive FIFO threshold = 8 */ 234*4882a593Smuzhiyun #define UART_FCR_PXAR16 0x80 /* receive FIFO threshold = 16 */ 235*4882a593Smuzhiyun #define UART_FCR_PXAR32 0xc0 /* receive FIFO threshold = 32 */ 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun /* 238*4882a593Smuzhiyun * Intel MID on-chip HSU (High Speed UART) defined bits 239*4882a593Smuzhiyun */ 240*4882a593Smuzhiyun #define UART_FCR_HSU_64_1B 0x00 /* receive FIFO treshold = 1 */ 241*4882a593Smuzhiyun #define UART_FCR_HSU_64_16B 0x40 /* receive FIFO treshold = 16 */ 242*4882a593Smuzhiyun #define UART_FCR_HSU_64_32B 0x80 /* receive FIFO treshold = 32 */ 243*4882a593Smuzhiyun #define UART_FCR_HSU_64_56B 0xc0 /* receive FIFO treshold = 56 */ 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun #define UART_FCR_HSU_16_1B 0x00 /* receive FIFO treshold = 1 */ 246*4882a593Smuzhiyun #define UART_FCR_HSU_16_4B 0x40 /* receive FIFO treshold = 4 */ 247*4882a593Smuzhiyun #define UART_FCR_HSU_16_8B 0x80 /* receive FIFO treshold = 8 */ 248*4882a593Smuzhiyun #define UART_FCR_HSU_16_14B 0xc0 /* receive FIFO treshold = 14 */ 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun #define UART_FCR_HSU_64B_FIFO 0x20 /* chose 64 bytes FIFO */ 251*4882a593Smuzhiyun #define UART_FCR_HSU_16B_FIFO 0x00 /* chose 16 bytes FIFO */ 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun #define UART_FCR_HALF_EMPT_TXI 0x00 /* trigger TX_EMPT IRQ for half empty */ 254*4882a593Smuzhiyun #define UART_FCR_FULL_EMPT_TXI 0x08 /* trigger TX_EMPT IRQ for full empty */ 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun /* 257*4882a593Smuzhiyun * These register definitions are for the 16C950 258*4882a593Smuzhiyun */ 259*4882a593Smuzhiyun #define UART_ASR 0x01 /* Additional Status Register */ 260*4882a593Smuzhiyun #define UART_RFL 0x03 /* Receiver FIFO level */ 261*4882a593Smuzhiyun #define UART_TFL 0x04 /* Transmitter FIFO level */ 262*4882a593Smuzhiyun #define UART_ICR 0x05 /* Index Control Register */ 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun /* The 16950 ICR registers */ 265*4882a593Smuzhiyun #define UART_ACR 0x00 /* Additional Control Register */ 266*4882a593Smuzhiyun #define UART_CPR 0x01 /* Clock Prescalar Register */ 267*4882a593Smuzhiyun #define UART_TCR 0x02 /* Times Clock Register */ 268*4882a593Smuzhiyun #define UART_CKS 0x03 /* Clock Select Register */ 269*4882a593Smuzhiyun #define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */ 270*4882a593Smuzhiyun #define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */ 271*4882a593Smuzhiyun #define UART_FCL 0x06 /* Flow Control Level Lower */ 272*4882a593Smuzhiyun #define UART_FCH 0x07 /* Flow Control Level Higher */ 273*4882a593Smuzhiyun #define UART_ID1 0x08 /* ID #1 */ 274*4882a593Smuzhiyun #define UART_ID2 0x09 /* ID #2 */ 275*4882a593Smuzhiyun #define UART_ID3 0x0A /* ID #3 */ 276*4882a593Smuzhiyun #define UART_REV 0x0B /* Revision */ 277*4882a593Smuzhiyun #define UART_CSR 0x0C /* Channel Software Reset */ 278*4882a593Smuzhiyun #define UART_NMR 0x0D /* Nine-bit Mode Register */ 279*4882a593Smuzhiyun #define UART_CTR 0xFF 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun /* 282*4882a593Smuzhiyun * The 16C950 Additional Control Register 283*4882a593Smuzhiyun */ 284*4882a593Smuzhiyun #define UART_ACR_RXDIS 0x01 /* Receiver disable */ 285*4882a593Smuzhiyun #define UART_ACR_TXDIS 0x02 /* Transmitter disable */ 286*4882a593Smuzhiyun #define UART_ACR_DSRFC 0x04 /* DSR Flow Control */ 287*4882a593Smuzhiyun #define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */ 288*4882a593Smuzhiyun #define UART_ACR_ICRRD 0x40 /* ICR Read enable */ 289*4882a593Smuzhiyun #define UART_ACR_ASREN 0x80 /* Additional status enable */ 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun /* 294*4882a593Smuzhiyun * These definitions are for the RSA-DV II/S card, from 295*4882a593Smuzhiyun * 296*4882a593Smuzhiyun * Kiyokazu SUTO <suto@ks-and-ks.ne.jp> 297*4882a593Smuzhiyun */ 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun #define UART_RSA_BASE (-8) 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun #define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */ 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun #define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */ 304*4882a593Smuzhiyun #define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */ 305*4882a593Smuzhiyun #define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */ 306*4882a593Smuzhiyun #define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */ 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun #define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */ 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun #define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */ 311*4882a593Smuzhiyun #define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */ 312*4882a593Smuzhiyun #define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */ 313*4882a593Smuzhiyun #define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */ 314*4882a593Smuzhiyun #define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */ 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun #define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */ 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun #define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */ 319*4882a593Smuzhiyun #define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */ 320*4882a593Smuzhiyun #define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */ 321*4882a593Smuzhiyun #define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */ 322*4882a593Smuzhiyun #define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */ 323*4882a593Smuzhiyun #define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */ 324*4882a593Smuzhiyun #define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */ 325*4882a593Smuzhiyun #define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */ 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun #define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */ 328*4882a593Smuzhiyun 329*4882a593Smuzhiyun #define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */ 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun #define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */ 332*4882a593Smuzhiyun 333*4882a593Smuzhiyun #define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */ 334*4882a593Smuzhiyun 335*4882a593Smuzhiyun /* 336*4882a593Smuzhiyun * The RSA DSV/II board has two fixed clock frequencies. One is the 337*4882a593Smuzhiyun * standard rate, and the other is 8 times faster. 338*4882a593Smuzhiyun */ 339*4882a593Smuzhiyun #define SERIAL_RSA_BAUD_BASE (921600) 340*4882a593Smuzhiyun #define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8) 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun /* 343*4882a593Smuzhiyun * Extra serial register definitions for the internal UARTs 344*4882a593Smuzhiyun * in TI OMAP processors. 345*4882a593Smuzhiyun */ 346*4882a593Smuzhiyun #define UART_OMAP_MDR1 0x08 /* Mode definition register */ 347*4882a593Smuzhiyun #define UART_OMAP_MDR2 0x09 /* Mode definition register 2 */ 348*4882a593Smuzhiyun #define UART_OMAP_SCR 0x10 /* Supplementary control register */ 349*4882a593Smuzhiyun #define UART_OMAP_SSR 0x11 /* Supplementary status register */ 350*4882a593Smuzhiyun #define UART_OMAP_EBLR 0x12 /* BOF length register */ 351*4882a593Smuzhiyun #define UART_OMAP_OSC_12M_SEL 0x13 /* OMAP1510 12MHz osc select */ 352*4882a593Smuzhiyun #define UART_OMAP_MVER 0x14 /* Module version register */ 353*4882a593Smuzhiyun #define UART_OMAP_SYSC 0x15 /* System configuration register */ 354*4882a593Smuzhiyun #define UART_OMAP_SYSS 0x16 /* System status register */ 355*4882a593Smuzhiyun #define UART_OMAP_WER 0x17 /* Wake-up enable register */ 356*4882a593Smuzhiyun 357*4882a593Smuzhiyun /* 358*4882a593Smuzhiyun * These are the definitions for the MDR1 register 359*4882a593Smuzhiyun */ 360*4882a593Smuzhiyun #define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */ 361*4882a593Smuzhiyun #define UART_OMAP_MDR1_SIR_MODE 0x01 /* SIR mode */ 362*4882a593Smuzhiyun #define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */ 363*4882a593Smuzhiyun #define UART_OMAP_MDR1_13X_MODE 0x03 /* UART 13x mode */ 364*4882a593Smuzhiyun #define UART_OMAP_MDR1_MIR_MODE 0x04 /* MIR mode */ 365*4882a593Smuzhiyun #define UART_OMAP_MDR1_FIR_MODE 0x05 /* FIR mode */ 366*4882a593Smuzhiyun #define UART_OMAP_MDR1_CIR_MODE 0x06 /* CIR mode */ 367*4882a593Smuzhiyun #define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */ 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun /* 370*4882a593Smuzhiyun * These are definitions for the Exar XR17V35X and XR17(C|D)15X 371*4882a593Smuzhiyun */ 372*4882a593Smuzhiyun #define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */ 373*4882a593Smuzhiyun #define UART_EXAR_SLEEP 0x8b /* Sleep mode */ 374*4882a593Smuzhiyun #define UART_EXAR_DVID 0x8d /* Device identification */ 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun #define UART_EXAR_FCTR 0x08 /* Feature Control Register */ 377*4882a593Smuzhiyun #define UART_FCTR_EXAR_IRDA 0x08 /* IrDa data encode select */ 378*4882a593Smuzhiyun #define UART_FCTR_EXAR_485 0x10 /* Auto 485 half duplex dir ctl */ 379*4882a593Smuzhiyun #define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */ 380*4882a593Smuzhiyun #define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */ 381*4882a593Smuzhiyun #define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */ 382*4882a593Smuzhiyun #define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */ 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */ 385*4882a593Smuzhiyun #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */ 386*4882a593Smuzhiyun 387*4882a593Smuzhiyun #endif /* _LINUX_SERIAL_REG_H */ 388*4882a593Smuzhiyun 389