1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2009 3*4882a593Smuzhiyun * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef ST_SMI_H 9*4882a593Smuzhiyun #define ST_SMI_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 0xF800.0000 . 0xFBFF.FFFF 64MB SMI (Serial Flash Mem) */ 12*4882a593Smuzhiyun /* 0xFC00.0000 . 0xFC1F.FFFF 2MB SMI (Serial Flash Reg.) */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define FLASH_START_ADDRESS CONFIG_SYS_FLASH_BASE 15*4882a593Smuzhiyun #define FLASH_BANK_SIZE CONFIG_SYS_FLASH_BANK_SIZE 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define SMIBANK0_BASE (FLASH_START_ADDRESS) 18*4882a593Smuzhiyun #define SMIBANK1_BASE (SMIBANK0_BASE + FLASH_BANK_SIZE) 19*4882a593Smuzhiyun #define SMIBANK2_BASE (SMIBANK1_BASE + FLASH_BANK_SIZE) 20*4882a593Smuzhiyun #define SMIBANK3_BASE (SMIBANK2_BASE + FLASH_BANK_SIZE) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define BANK0 0 23*4882a593Smuzhiyun #define BANK1 1 24*4882a593Smuzhiyun #define BANK2 2 25*4882a593Smuzhiyun #define BANK3 3 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun struct smi_regs { 28*4882a593Smuzhiyun u32 smi_cr1; 29*4882a593Smuzhiyun u32 smi_cr2; 30*4882a593Smuzhiyun u32 smi_sr; 31*4882a593Smuzhiyun u32 smi_tr; 32*4882a593Smuzhiyun u32 smi_rr; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* CONTROL REG 1 */ 36*4882a593Smuzhiyun #define BANK_EN 0x0000000F /* enables all banks */ 37*4882a593Smuzhiyun #define DSEL_TIME 0x00000060 /* Deselect time */ 38*4882a593Smuzhiyun #define PRESCAL5 0x00000500 /* AHB_CK prescaling value */ 39*4882a593Smuzhiyun #define PRESCALA 0x00000A00 /* AHB_CK prescaling value */ 40*4882a593Smuzhiyun #define PRESCAL3 0x00000300 /* AHB_CK prescaling value */ 41*4882a593Smuzhiyun #define PRESCAL4 0x00000400 /* AHB_CK prescaling value */ 42*4882a593Smuzhiyun #define SW_MODE 0x10000000 /* enables SW Mode */ 43*4882a593Smuzhiyun #define WB_MODE 0x20000000 /* Write Burst Mode */ 44*4882a593Smuzhiyun #define FAST_MODE 0x00008000 /* Fast Mode */ 45*4882a593Smuzhiyun #define HOLD1 0x00010000 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* CONTROL REG 2 */ 48*4882a593Smuzhiyun #define RD_STATUS_REG 0x00000400 /* reads status reg */ 49*4882a593Smuzhiyun #define WE 0x00000800 /* Write Enable */ 50*4882a593Smuzhiyun #define BANK0_SEL 0x00000000 /* Select Banck0 */ 51*4882a593Smuzhiyun #define BANK1_SEL 0x00001000 /* Select Banck1 */ 52*4882a593Smuzhiyun #define BANK2_SEL 0x00002000 /* Select Banck2 */ 53*4882a593Smuzhiyun #define BANK3_SEL 0x00003000 /* Select Banck3 */ 54*4882a593Smuzhiyun #define BANKSEL_SHIFT 12 55*4882a593Smuzhiyun #define SEND 0x00000080 /* Send data */ 56*4882a593Smuzhiyun #define TX_LEN_1 0x00000001 /* data length = 1 byte */ 57*4882a593Smuzhiyun #define TX_LEN_2 0x00000002 /* data length = 2 byte */ 58*4882a593Smuzhiyun #define TX_LEN_3 0x00000003 /* data length = 3 byte */ 59*4882a593Smuzhiyun #define TX_LEN_4 0x00000004 /* data length = 4 byte */ 60*4882a593Smuzhiyun #define RX_LEN_1 0x00000010 /* data length = 1 byte */ 61*4882a593Smuzhiyun #define RX_LEN_2 0x00000020 /* data length = 2 byte */ 62*4882a593Smuzhiyun #define RX_LEN_3 0x00000030 /* data length = 3 byte */ 63*4882a593Smuzhiyun #define RX_LEN_4 0x00000040 /* data length = 4 byte */ 64*4882a593Smuzhiyun #define TFIE 0x00000100 /* Tx Flag Interrupt Enable */ 65*4882a593Smuzhiyun #define WCIE 0x00000200 /* WCF Interrupt Enable */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* STATUS_REG */ 68*4882a593Smuzhiyun #define INT_WCF_CLR 0xFFFFFDFF /* clear: WCF clear */ 69*4882a593Smuzhiyun #define INT_TFF_CLR 0xFFFFFEFF /* clear: TFF clear */ 70*4882a593Smuzhiyun #define WIP_BIT 0x00000001 /* WIP Bit of SPI SR */ 71*4882a593Smuzhiyun #define WEL_BIT 0x00000002 /* WEL Bit of SPI SR */ 72*4882a593Smuzhiyun #define RSR 0x00000005 /* Read Status regiser */ 73*4882a593Smuzhiyun #define TFF 0x00000100 /* Transfer Finished FLag */ 74*4882a593Smuzhiyun #define WCF 0x00000200 /* Transfer Finished FLag */ 75*4882a593Smuzhiyun #define ERF1 0x00000400 /* Error Flag 1 */ 76*4882a593Smuzhiyun #define ERF2 0x00000800 /* Error Flag 2 */ 77*4882a593Smuzhiyun #define WM0 0x00001000 /* WM Bank 0 */ 78*4882a593Smuzhiyun #define WM1 0x00002000 /* WM Bank 1 */ 79*4882a593Smuzhiyun #define WM2 0x00004000 /* WM Bank 2 */ 80*4882a593Smuzhiyun #define WM3 0x00008000 /* WM Bank 3 */ 81*4882a593Smuzhiyun #define WM_SHIFT 12 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* TR REG */ 84*4882a593Smuzhiyun #define READ_ID 0x0000009F /* Read Identification */ 85*4882a593Smuzhiyun #define BULK_ERASE 0x000000C7 /* BULK erase */ 86*4882a593Smuzhiyun #define SECTOR_ERASE 0x000000D8 /* SECTOR erase */ 87*4882a593Smuzhiyun #define WRITE_ENABLE 0x00000006 /* Wenable command to FLASH */ 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun struct flash_dev { 90*4882a593Smuzhiyun u32 density; 91*4882a593Smuzhiyun ulong size; 92*4882a593Smuzhiyun ushort sector_count; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define SFLASH_PAGE_SIZE 0x100 /* flash page size */ 96*4882a593Smuzhiyun #define XFER_FINISH_TOUT 15 /* xfer finish timeout(in ms) */ 97*4882a593Smuzhiyun #define WMODE_TOUT 15 /* write enable timeout(in ms) */ 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun extern void smi_init(void); 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #endif 102