1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2005-2009 Samsung Electronics 3*4882a593Smuzhiyun * Minkyu Kang <mk7.kang@samsung.com> 4*4882a593Smuzhiyun * Kyungmin Park <kyungmin.park@samsung.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __SAMSUNG_ONENAND_H__ 10*4882a593Smuzhiyun #define __SAMSUNG_ONENAND_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * OneNAND Controller 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 17*4882a593Smuzhiyun struct samsung_onenand { 18*4882a593Smuzhiyun unsigned int mem_cfg; /* 0x0000 */ 19*4882a593Smuzhiyun unsigned char res1[0xc]; 20*4882a593Smuzhiyun unsigned int burst_len; /* 0x0010 */ 21*4882a593Smuzhiyun unsigned char res2[0xc]; 22*4882a593Smuzhiyun unsigned int mem_reset; /* 0x0020 */ 23*4882a593Smuzhiyun unsigned char res3[0xc]; 24*4882a593Smuzhiyun unsigned int int_err_stat; /* 0x0030 */ 25*4882a593Smuzhiyun unsigned char res4[0xc]; 26*4882a593Smuzhiyun unsigned int int_err_mask; /* 0x0040 */ 27*4882a593Smuzhiyun unsigned char res5[0xc]; 28*4882a593Smuzhiyun unsigned int int_err_ack; /* 0x0050 */ 29*4882a593Smuzhiyun unsigned char res6[0xc]; 30*4882a593Smuzhiyun unsigned int ecc_err_stat; /* 0x0060 */ 31*4882a593Smuzhiyun unsigned char res7[0xc]; 32*4882a593Smuzhiyun unsigned int manufact_id; /* 0x0070 */ 33*4882a593Smuzhiyun unsigned char res8[0xc]; 34*4882a593Smuzhiyun unsigned int device_id; /* 0x0080 */ 35*4882a593Smuzhiyun unsigned char res9[0xc]; 36*4882a593Smuzhiyun unsigned int data_buf_size; /* 0x0090 */ 37*4882a593Smuzhiyun unsigned char res10[0xc]; 38*4882a593Smuzhiyun unsigned int boot_buf_size; /* 0x00A0 */ 39*4882a593Smuzhiyun unsigned char res11[0xc]; 40*4882a593Smuzhiyun unsigned int buf_amount; /* 0x00B0 */ 41*4882a593Smuzhiyun unsigned char res12[0xc]; 42*4882a593Smuzhiyun unsigned int tech; /* 0x00C0 */ 43*4882a593Smuzhiyun unsigned char res13[0xc]; 44*4882a593Smuzhiyun unsigned int fba; /* 0x00D0 */ 45*4882a593Smuzhiyun unsigned char res14[0xc]; 46*4882a593Smuzhiyun unsigned int fpa; /* 0x00E0 */ 47*4882a593Smuzhiyun unsigned char res15[0xc]; 48*4882a593Smuzhiyun unsigned int fsa; /* 0x00F0 */ 49*4882a593Smuzhiyun unsigned char res16[0x3c]; 50*4882a593Smuzhiyun unsigned int sync_mode; /* 0x0130 */ 51*4882a593Smuzhiyun unsigned char res17[0xc]; 52*4882a593Smuzhiyun unsigned int trans_spare; /* 0x0140 */ 53*4882a593Smuzhiyun unsigned char res18[0x3c]; 54*4882a593Smuzhiyun unsigned int err_page_addr; /* 0x0180 */ 55*4882a593Smuzhiyun unsigned char res19[0x1c]; 56*4882a593Smuzhiyun unsigned int int_pin_en; /* 0x01A0 */ 57*4882a593Smuzhiyun unsigned char res20[0x1c]; 58*4882a593Smuzhiyun unsigned int acc_clock; /* 0x01C0 */ 59*4882a593Smuzhiyun unsigned char res21[0x1c]; 60*4882a593Smuzhiyun unsigned int err_blk_addr; /* 0x01E0 */ 61*4882a593Smuzhiyun unsigned char res22[0xc]; 62*4882a593Smuzhiyun unsigned int flash_ver_id; /* 0x01F0 */ 63*4882a593Smuzhiyun unsigned char res23[0x6c]; 64*4882a593Smuzhiyun unsigned int watchdog_cnt_low; /* 0x0260 */ 65*4882a593Smuzhiyun unsigned char res24[0xc]; 66*4882a593Smuzhiyun unsigned int watchdog_cnt_hi; /* 0x0270 */ 67*4882a593Smuzhiyun unsigned char res25[0xc]; 68*4882a593Smuzhiyun unsigned int sync_write; /* 0x0280 */ 69*4882a593Smuzhiyun unsigned char res26[0x1c]; 70*4882a593Smuzhiyun unsigned int cold_reset; /* 0x02A0 */ 71*4882a593Smuzhiyun unsigned char res27[0xc]; 72*4882a593Smuzhiyun unsigned int ddp_device; /* 0x02B0 */ 73*4882a593Smuzhiyun unsigned char res28[0xc]; 74*4882a593Smuzhiyun unsigned int multi_plane; /* 0x02C0 */ 75*4882a593Smuzhiyun unsigned char res29[0x1c]; 76*4882a593Smuzhiyun unsigned int trans_mode; /* 0x02E0 */ 77*4882a593Smuzhiyun unsigned char res30[0x1c]; 78*4882a593Smuzhiyun unsigned int ecc_err_stat2; /* 0x0300 */ 79*4882a593Smuzhiyun unsigned char res31[0xc]; 80*4882a593Smuzhiyun unsigned int ecc_err_stat3; /* 0x0310 */ 81*4882a593Smuzhiyun unsigned char res32[0xc]; 82*4882a593Smuzhiyun unsigned int ecc_err_stat4; /* 0x0320 */ 83*4882a593Smuzhiyun unsigned char res33[0x1c]; 84*4882a593Smuzhiyun unsigned int dev_page_size; /* 0x0340 */ 85*4882a593Smuzhiyun unsigned char res34[0x4c]; 86*4882a593Smuzhiyun unsigned int int_mon_status; /* 0x0390 */ 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun #endif 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define ONENAND_MEM_RESET_HOT 0x3 91*4882a593Smuzhiyun #define ONENAND_MEM_RESET_COLD 0x2 92*4882a593Smuzhiyun #define ONENAND_MEM_RESET_WARM 0x1 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define INT_ERR_ALL 0x3fff 95*4882a593Smuzhiyun #define CACHE_OP_ERR (1 << 13) 96*4882a593Smuzhiyun #define RST_CMP (1 << 12) 97*4882a593Smuzhiyun #define RDY_ACT (1 << 11) 98*4882a593Smuzhiyun #define INT_ACT (1 << 10) 99*4882a593Smuzhiyun #define UNSUP_CMD (1 << 9) 100*4882a593Smuzhiyun #define LOCKED_BLK (1 << 8) 101*4882a593Smuzhiyun #define BLK_RW_CMP (1 << 7) 102*4882a593Smuzhiyun #define ERS_CMP (1 << 6) 103*4882a593Smuzhiyun #define PGM_CMP (1 << 5) 104*4882a593Smuzhiyun #define LOAD_CMP (1 << 4) 105*4882a593Smuzhiyun #define ERS_FAIL (1 << 3) 106*4882a593Smuzhiyun #define PGM_FAIL (1 << 2) 107*4882a593Smuzhiyun #define INT_TO (1 << 1) 108*4882a593Smuzhiyun #define LD_FAIL_ECC_ERR (1 << 0) 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #define TSRF (1 << 0) 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* common initialize function */ 113*4882a593Smuzhiyun extern void s3c_onenand_init(struct mtd_info *); 114*4882a593Smuzhiyun extern int s5pc110_chip_probe(struct mtd_info *); 115*4882a593Smuzhiyun extern int s5pc210_chip_probe(struct mtd_info *); 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #endif 118