1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com> 3*4882a593Smuzhiyun * Rohit Choraria <rohitkc@ti.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * (C) Copyright 2013 Andreas Bießmann <andreas@biessmann.org> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef __ASM_OMAP_GPMC_H 10*4882a593Smuzhiyun #define __ASM_OMAP_GPMC_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define GPMC_BUF_EMPTY 0 13*4882a593Smuzhiyun #define GPMC_BUF_FULL 1 14*4882a593Smuzhiyun #define GPMC_MAX_SECTORS 8 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun enum omap_ecc { 17*4882a593Smuzhiyun /* 1-bit ECC calculation by Software, Error detection by Software */ 18*4882a593Smuzhiyun OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */ 19*4882a593Smuzhiyun /* 1-bit ECC calculation by GPMC, Error detection by Software */ 20*4882a593Smuzhiyun /* ECC layout compatible to legacy ROMCODE. */ 21*4882a593Smuzhiyun OMAP_ECC_HAM1_CODE_HW, 22*4882a593Smuzhiyun /* 4-bit ECC calculation by GPMC, Error detection by Software */ 23*4882a593Smuzhiyun OMAP_ECC_BCH4_CODE_HW_DETECTION_SW, 24*4882a593Smuzhiyun /* 4-bit ECC calculation by GPMC, Error detection by ELM */ 25*4882a593Smuzhiyun OMAP_ECC_BCH4_CODE_HW, 26*4882a593Smuzhiyun /* 8-bit ECC calculation by GPMC, Error detection by Software */ 27*4882a593Smuzhiyun OMAP_ECC_BCH8_CODE_HW_DETECTION_SW, 28*4882a593Smuzhiyun /* 8-bit ECC calculation by GPMC, Error detection by ELM */ 29*4882a593Smuzhiyun OMAP_ECC_BCH8_CODE_HW, 30*4882a593Smuzhiyun /* 16-bit ECC calculation by GPMC, Error detection by ELM */ 31*4882a593Smuzhiyun OMAP_ECC_BCH16_CODE_HW, 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun struct gpmc_cs { 35*4882a593Smuzhiyun u32 config1; /* 0x00 */ 36*4882a593Smuzhiyun u32 config2; /* 0x04 */ 37*4882a593Smuzhiyun u32 config3; /* 0x08 */ 38*4882a593Smuzhiyun u32 config4; /* 0x0C */ 39*4882a593Smuzhiyun u32 config5; /* 0x10 */ 40*4882a593Smuzhiyun u32 config6; /* 0x14 */ 41*4882a593Smuzhiyun u32 config7; /* 0x18 */ 42*4882a593Smuzhiyun u32 nand_cmd; /* 0x1C */ 43*4882a593Smuzhiyun u32 nand_adr; /* 0x20 */ 44*4882a593Smuzhiyun u32 nand_dat; /* 0x24 */ 45*4882a593Smuzhiyun u8 res[8]; /* blow up to 0x30 byte */ 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun struct bch_res_0_3 { 49*4882a593Smuzhiyun u32 bch_result_x[4]; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun struct bch_res_4_6 { 53*4882a593Smuzhiyun u32 bch_result_x[3]; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun struct gpmc { 57*4882a593Smuzhiyun u8 res1[0x10]; 58*4882a593Smuzhiyun u32 sysconfig; /* 0x10 */ 59*4882a593Smuzhiyun u8 res2[0x4]; 60*4882a593Smuzhiyun u32 irqstatus; /* 0x18 */ 61*4882a593Smuzhiyun u32 irqenable; /* 0x1C */ 62*4882a593Smuzhiyun u8 res3[0x20]; 63*4882a593Smuzhiyun u32 timeout_control; /* 0x40 */ 64*4882a593Smuzhiyun u8 res4[0xC]; 65*4882a593Smuzhiyun u32 config; /* 0x50 */ 66*4882a593Smuzhiyun u32 status; /* 0x54 */ 67*4882a593Smuzhiyun u8 res5[0x8]; /* 0x58 */ 68*4882a593Smuzhiyun struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ 69*4882a593Smuzhiyun u32 prefetch_config1; /* 0x1E0 */ 70*4882a593Smuzhiyun u32 prefetch_config2; /* 0x1E4 */ 71*4882a593Smuzhiyun u32 res6; /* 0x1E8 */ 72*4882a593Smuzhiyun u32 prefetch_control; /* 0x1EC */ 73*4882a593Smuzhiyun u32 prefetch_status; /* 0x1F0 */ 74*4882a593Smuzhiyun u32 ecc_config; /* 0x1F4 */ 75*4882a593Smuzhiyun u32 ecc_control; /* 0x1F8 */ 76*4882a593Smuzhiyun u32 ecc_size_config; /* 0x1FC */ 77*4882a593Smuzhiyun u32 ecc1_result; /* 0x200 */ 78*4882a593Smuzhiyun u32 ecc2_result; /* 0x204 */ 79*4882a593Smuzhiyun u32 ecc3_result; /* 0x208 */ 80*4882a593Smuzhiyun u32 ecc4_result; /* 0x20C */ 81*4882a593Smuzhiyun u32 ecc5_result; /* 0x210 */ 82*4882a593Smuzhiyun u32 ecc6_result; /* 0x214 */ 83*4882a593Smuzhiyun u32 ecc7_result; /* 0x218 */ 84*4882a593Smuzhiyun u32 ecc8_result; /* 0x21C */ 85*4882a593Smuzhiyun u32 ecc9_result; /* 0x220 */ 86*4882a593Smuzhiyun u8 res7[12]; /* 0x224 */ 87*4882a593Smuzhiyun u32 testmomde_ctrl; /* 0x230 */ 88*4882a593Smuzhiyun u8 res8[12]; /* 0x234 */ 89*4882a593Smuzhiyun struct bch_res_0_3 bch_result_0_3[GPMC_MAX_SECTORS]; /* 0x240,0x250, */ 90*4882a593Smuzhiyun u8 res9[16 * 4]; /* 0x2C0 - 0x2FF */ 91*4882a593Smuzhiyun struct bch_res_4_6 bch_result_4_6[GPMC_MAX_SECTORS]; /* 0x300,0x310, */ 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* Used for board specific gpmc initialization */ 95*4882a593Smuzhiyun extern const struct gpmc *gpmc_cfg; 96*4882a593Smuzhiyun extern char gpmc_cs0_flash; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #endif /* __ASM_OMAP_GPMC_H */ 99