1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010 3*4882a593Smuzhiyun * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __FSMC_NAND_H__ 9*4882a593Smuzhiyun #define __FSMC_NAND_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/mtd/rawnand.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct fsmc_regs { 14*4882a593Smuzhiyun u32 ctrl; /* 0x00 */ 15*4882a593Smuzhiyun u8 reserved_1[0x40 - 0x04]; 16*4882a593Smuzhiyun u32 pc; /* 0x40 */ 17*4882a593Smuzhiyun u32 sts; /* 0x44 */ 18*4882a593Smuzhiyun u32 comm; /* 0x48 */ 19*4882a593Smuzhiyun u32 attrib; /* 0x4c */ 20*4882a593Smuzhiyun u32 ioata; /* 0x50 */ 21*4882a593Smuzhiyun u32 ecc1; /* 0x54 */ 22*4882a593Smuzhiyun u32 ecc2; /* 0x58 */ 23*4882a593Smuzhiyun u32 ecc3; /* 0x5c */ 24*4882a593Smuzhiyun u8 reserved_2[0xfe0 - 0x60]; 25*4882a593Smuzhiyun u32 peripid0; /* 0xfe0 */ 26*4882a593Smuzhiyun u32 peripid1; /* 0xfe4 */ 27*4882a593Smuzhiyun u32 peripid2; /* 0xfe8 */ 28*4882a593Smuzhiyun u32 peripid3; /* 0xfec */ 29*4882a593Smuzhiyun u32 pcellid0; /* 0xff0 */ 30*4882a593Smuzhiyun u32 pcellid1; /* 0xff4 */ 31*4882a593Smuzhiyun u32 pcellid2; /* 0xff8 */ 32*4882a593Smuzhiyun u32 pcellid3; /* 0xffc */ 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* ctrl register definitions */ 36*4882a593Smuzhiyun #define FSMC_WP (1 << 7) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* pc register definitions */ 39*4882a593Smuzhiyun #define FSMC_RESET (1 << 0) 40*4882a593Smuzhiyun #define FSMC_WAITON (1 << 1) 41*4882a593Smuzhiyun #define FSMC_ENABLE (1 << 2) 42*4882a593Smuzhiyun #define FSMC_DEVTYPE_NAND (1 << 3) 43*4882a593Smuzhiyun #define FSMC_DEVWID_8 (0 << 4) 44*4882a593Smuzhiyun #define FSMC_DEVWID_16 (1 << 4) 45*4882a593Smuzhiyun #define FSMC_ECCEN (1 << 6) 46*4882a593Smuzhiyun #define FSMC_ECCPLEN_512 (0 << 7) 47*4882a593Smuzhiyun #define FSMC_ECCPLEN_256 (1 << 7) 48*4882a593Smuzhiyun #define FSMC_TCLR_1 (1 << 9) 49*4882a593Smuzhiyun #define FSMC_TAR_1 (1 << 13) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* sts register definitions */ 52*4882a593Smuzhiyun #define FSMC_CODE_RDY (1 << 15) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* comm register definitions */ 55*4882a593Smuzhiyun #define FSMC_TSET_0 (0 << 0) 56*4882a593Smuzhiyun #define FSMC_TWAIT_6 (6 << 8) 57*4882a593Smuzhiyun #define FSMC_THOLD_4 (4 << 16) 58*4882a593Smuzhiyun #define FSMC_THIZ_1 (1 << 24) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* peripid2 register definitions */ 61*4882a593Smuzhiyun #define FSMC_REVISION_MSK (0xf) 62*4882a593Smuzhiyun #define FSMC_REVISION_SHFT (0x4) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define FSMC_VER8 0x8 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* 67*4882a593Smuzhiyun * There are 13 bytes of ecc for every 512 byte block and it has to be read 68*4882a593Smuzhiyun * consecutively and immediately after the 512 byte data block for hardware to 69*4882a593Smuzhiyun * generate the error bit offsets 70*4882a593Smuzhiyun * Managing the ecc bytes in the following way is easier. This way is similar to 71*4882a593Smuzhiyun * oobfree structure maintained already in u-boot nand driver 72*4882a593Smuzhiyun */ 73*4882a593Smuzhiyun #define FSMC_MAX_ECCPLACE_ENTRIES 32 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun struct fsmc_nand_eccplace { 76*4882a593Smuzhiyun u32 offset; 77*4882a593Smuzhiyun u32 length; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun struct fsmc_eccplace { 81*4882a593Smuzhiyun struct fsmc_nand_eccplace eccplace[FSMC_MAX_ECCPLACE_ENTRIES]; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun extern int fsmc_nand_init(struct nand_chip *nand); 85*4882a593Smuzhiyun #endif 86