1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * FSL UPM NAND driver 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2007 MontaVista Software, Inc. 5*4882a593Smuzhiyun * Anton Vorontsov <avorontsov@ru.mvista.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __LINUX_MTD_NAND_FSL_UPM 11*4882a593Smuzhiyun #define __LINUX_MTD_NAND_FSL_UPM 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/mtd/rawnand.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define FSL_UPM_WAIT_RUN_PATTERN 0x1 16*4882a593Smuzhiyun #define FSL_UPM_WAIT_WRITE_BYTE 0x2 17*4882a593Smuzhiyun #define FSL_UPM_WAIT_WRITE_BUFFER 0x4 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun struct fsl_upm { 20*4882a593Smuzhiyun void __iomem *mdr; 21*4882a593Smuzhiyun void __iomem *mxmr; 22*4882a593Smuzhiyun void __iomem *mar; 23*4882a593Smuzhiyun void __iomem *io_addr; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun struct fsl_upm_nand { 27*4882a593Smuzhiyun struct fsl_upm upm; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun int width; 30*4882a593Smuzhiyun int upm_cmd_offset; 31*4882a593Smuzhiyun int upm_addr_offset; 32*4882a593Smuzhiyun int upm_mar_chip_offset; 33*4882a593Smuzhiyun int wait_flags; 34*4882a593Smuzhiyun int (*dev_ready)(int chip_nr); 35*4882a593Smuzhiyun int chip_delay; 36*4882a593Smuzhiyun int chip_offset; 37*4882a593Smuzhiyun int chip_nr; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* no need to fill */ 40*4882a593Smuzhiyun int last_ctrl; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun extern int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun); 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #endif 46