1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * linux/mii.h: definitions for MII-compatible transceivers
4*4882a593Smuzhiyun * Originally drivers/net/sunhme.h.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 1996, 1999, 2001 David S. Miller (davem@redhat.com)
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifndef __LINUX_MII_H__
10*4882a593Smuzhiyun #define __LINUX_MII_H__
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun /* Generic MII registers. */
13*4882a593Smuzhiyun #define MII_BMCR 0x00 /* Basic mode control register */
14*4882a593Smuzhiyun #define MII_BMSR 0x01 /* Basic mode status register */
15*4882a593Smuzhiyun #define MII_PHYSID1 0x02 /* PHYS ID 1 */
16*4882a593Smuzhiyun #define MII_PHYSID2 0x03 /* PHYS ID 2 */
17*4882a593Smuzhiyun #define MII_ADVERTISE 0x04 /* Advertisement control reg */
18*4882a593Smuzhiyun #define MII_LPA 0x05 /* Link partner ability reg */
19*4882a593Smuzhiyun #define MII_EXPANSION 0x06 /* Expansion register */
20*4882a593Smuzhiyun #define MII_CTRL1000 0x09 /* 1000BASE-T control */
21*4882a593Smuzhiyun #define MII_STAT1000 0x0a /* 1000BASE-T status */
22*4882a593Smuzhiyun #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
23*4882a593Smuzhiyun #define MII_MMD_DATA 0x0e /* MMD Access Data Register */
24*4882a593Smuzhiyun #define MII_ESTATUS 0x0f /* Extended Status */
25*4882a593Smuzhiyun #define MII_DCOUNTER 0x12 /* Disconnect counter */
26*4882a593Smuzhiyun #define MII_FCSCOUNTER 0x13 /* False carrier counter */
27*4882a593Smuzhiyun #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
28*4882a593Smuzhiyun #define MII_RERRCOUNTER 0x15 /* Receive error counter */
29*4882a593Smuzhiyun #define MII_SREVISION 0x16 /* Silicon revision */
30*4882a593Smuzhiyun #define MII_RESV1 0x17 /* Reserved... */
31*4882a593Smuzhiyun #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
32*4882a593Smuzhiyun #define MII_PHYADDR 0x19 /* PHY address */
33*4882a593Smuzhiyun #define MII_RESV2 0x1a /* Reserved... */
34*4882a593Smuzhiyun #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
35*4882a593Smuzhiyun #define MII_NCONFIG 0x1c /* Network interface config */
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* Basic mode control register. */
38*4882a593Smuzhiyun #define BMCR_RESV 0x003f /* Unused... */
39*4882a593Smuzhiyun #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
40*4882a593Smuzhiyun #define BMCR_CTST 0x0080 /* Collision test */
41*4882a593Smuzhiyun #define BMCR_FULLDPLX 0x0100 /* Full duplex */
42*4882a593Smuzhiyun #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
43*4882a593Smuzhiyun #define BMCR_ISOLATE 0x0400 /* Isolate data paths from MII */
44*4882a593Smuzhiyun #define BMCR_PDOWN 0x0800 /* Enable low power state */
45*4882a593Smuzhiyun #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
46*4882a593Smuzhiyun #define BMCR_SPEED100 0x2000 /* Select 100Mbps */
47*4882a593Smuzhiyun #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
48*4882a593Smuzhiyun #define BMCR_RESET 0x8000 /* Reset to default state */
49*4882a593Smuzhiyun #define BMCR_SPEED10 0x0000 /* Select 10Mbps */
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /* Basic mode status register. */
52*4882a593Smuzhiyun #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
53*4882a593Smuzhiyun #define BMSR_JCD 0x0002 /* Jabber detected */
54*4882a593Smuzhiyun #define BMSR_LSTATUS 0x0004 /* Link status */
55*4882a593Smuzhiyun #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
56*4882a593Smuzhiyun #define BMSR_RFAULT 0x0010 /* Remote fault detected */
57*4882a593Smuzhiyun #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
58*4882a593Smuzhiyun #define BMSR_RESV 0x00c0 /* Unused... */
59*4882a593Smuzhiyun #define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
60*4882a593Smuzhiyun #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
61*4882a593Smuzhiyun #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
62*4882a593Smuzhiyun #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
63*4882a593Smuzhiyun #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
64*4882a593Smuzhiyun #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
65*4882a593Smuzhiyun #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
66*4882a593Smuzhiyun #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* Advertisement control register. */
69*4882a593Smuzhiyun #define ADVERTISE_SLCT 0x001f /* Selector bits */
70*4882a593Smuzhiyun #define ADVERTISE_CSMA 0x0001 /* Only selector supported */
71*4882a593Smuzhiyun #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
72*4882a593Smuzhiyun #define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
73*4882a593Smuzhiyun #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
74*4882a593Smuzhiyun #define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
75*4882a593Smuzhiyun #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
76*4882a593Smuzhiyun #define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
77*4882a593Smuzhiyun #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
78*4882a593Smuzhiyun #define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
79*4882a593Smuzhiyun #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
80*4882a593Smuzhiyun #define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
81*4882a593Smuzhiyun #define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
82*4882a593Smuzhiyun #define ADVERTISE_RESV 0x1000 /* Unused... */
83*4882a593Smuzhiyun #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
84*4882a593Smuzhiyun #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
85*4882a593Smuzhiyun #define ADVERTISE_NPAGE 0x8000 /* Next page bit */
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
88*4882a593Smuzhiyun ADVERTISE_CSMA)
89*4882a593Smuzhiyun #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
90*4882a593Smuzhiyun ADVERTISE_100HALF | ADVERTISE_100FULL)
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /* Link partner ability register. */
93*4882a593Smuzhiyun #define LPA_SLCT 0x001f /* Same as advertise selector */
94*4882a593Smuzhiyun #define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
95*4882a593Smuzhiyun #define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
96*4882a593Smuzhiyun #define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
97*4882a593Smuzhiyun #define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
98*4882a593Smuzhiyun #define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
99*4882a593Smuzhiyun #define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
100*4882a593Smuzhiyun #define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
101*4882a593Smuzhiyun #define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/
102*4882a593Smuzhiyun #define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
103*4882a593Smuzhiyun #define LPA_PAUSE_CAP 0x0400 /* Can pause */
104*4882a593Smuzhiyun #define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
105*4882a593Smuzhiyun #define LPA_RESV 0x1000 /* Unused... */
106*4882a593Smuzhiyun #define LPA_RFAULT 0x2000 /* Link partner faulted */
107*4882a593Smuzhiyun #define LPA_LPACK 0x4000 /* Link partner acked us */
108*4882a593Smuzhiyun #define LPA_NPAGE 0x8000 /* Next page bit */
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun #define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
111*4882a593Smuzhiyun #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /* Expansion register for auto-negotiation. */
114*4882a593Smuzhiyun #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
115*4882a593Smuzhiyun #define EXPANSION_LCWP 0x0002 /* Got new RX page code word */
116*4882a593Smuzhiyun #define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
117*4882a593Smuzhiyun #define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
118*4882a593Smuzhiyun #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
119*4882a593Smuzhiyun #define EXPANSION_RESV 0xffe0 /* Unused... */
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun #define ESTATUS_1000_XFULL 0x8000 /* Can do 1000BX Full */
122*4882a593Smuzhiyun #define ESTATUS_1000_XHALF 0x4000 /* Can do 1000BX Half */
123*4882a593Smuzhiyun #define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
124*4882a593Smuzhiyun #define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun /* N-way test register. */
127*4882a593Smuzhiyun #define NWAYTEST_RESV1 0x00ff /* Unused... */
128*4882a593Smuzhiyun #define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
129*4882a593Smuzhiyun #define NWAYTEST_RESV2 0xfe00 /* Unused... */
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun /* 1000BASE-T Control register */
132*4882a593Smuzhiyun #define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
133*4882a593Smuzhiyun #define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
134*4882a593Smuzhiyun #define CTL1000_AS_MASTER 0x0800
135*4882a593Smuzhiyun #define CTL1000_ENABLE_MASTER 0x1000
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun /* 1000BASE-T Status register */
138*4882a593Smuzhiyun #define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
139*4882a593Smuzhiyun #define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */
140*4882a593Smuzhiyun #define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */
141*4882a593Smuzhiyun #define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun /* Flow control flags */
144*4882a593Smuzhiyun #define FLOW_CTRL_TX 0x01
145*4882a593Smuzhiyun #define FLOW_CTRL_RX 0x02
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun /* MMD Access Control register fields */
148*4882a593Smuzhiyun #define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/
149*4882a593Smuzhiyun #define MII_MMD_CTRL_ADDR 0x0000 /* Address */
150*4882a593Smuzhiyun #define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */
151*4882a593Smuzhiyun #define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */
152*4882a593Smuzhiyun #define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun /**
155*4882a593Smuzhiyun * mii_nway_result
156*4882a593Smuzhiyun * @negotiated: value of MII ANAR and'd with ANLPAR
157*4882a593Smuzhiyun *
158*4882a593Smuzhiyun * Given a set of MII abilities, check each bit and returns the
159*4882a593Smuzhiyun * currently supported media, in the priority order defined by
160*4882a593Smuzhiyun * IEEE 802.3u. We use LPA_xxx constants but note this is not the
161*4882a593Smuzhiyun * value of LPA solely, as described above.
162*4882a593Smuzhiyun *
163*4882a593Smuzhiyun * The one exception to IEEE 802.3u is that 100baseT4 is placed
164*4882a593Smuzhiyun * between 100T-full and 100T-half. If your phy does not support
165*4882a593Smuzhiyun * 100T4 this is fine. If your phy places 100T4 elsewhere in the
166*4882a593Smuzhiyun * priority order, you will need to roll your own function.
167*4882a593Smuzhiyun */
mii_nway_result(unsigned int negotiated)168*4882a593Smuzhiyun static inline unsigned int mii_nway_result (unsigned int negotiated)
169*4882a593Smuzhiyun {
170*4882a593Smuzhiyun unsigned int ret;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun if (negotiated & LPA_100FULL)
173*4882a593Smuzhiyun ret = LPA_100FULL;
174*4882a593Smuzhiyun else if (negotiated & LPA_100BASE4)
175*4882a593Smuzhiyun ret = LPA_100BASE4;
176*4882a593Smuzhiyun else if (negotiated & LPA_100HALF)
177*4882a593Smuzhiyun ret = LPA_100HALF;
178*4882a593Smuzhiyun else if (negotiated & LPA_10FULL)
179*4882a593Smuzhiyun ret = LPA_10FULL;
180*4882a593Smuzhiyun else
181*4882a593Smuzhiyun ret = LPA_10HALF;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun return ret;
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun /**
187*4882a593Smuzhiyun * mii_duplex
188*4882a593Smuzhiyun * @duplex_lock: Non-zero if duplex is locked at full
189*4882a593Smuzhiyun * @negotiated: value of MII ANAR and'd with ANLPAR
190*4882a593Smuzhiyun *
191*4882a593Smuzhiyun * A small helper function for a common case. Returns one
192*4882a593Smuzhiyun * if the media is operating or locked at full duplex, and
193*4882a593Smuzhiyun * returns zero otherwise.
194*4882a593Smuzhiyun */
mii_duplex(unsigned int duplex_lock,unsigned int negotiated)195*4882a593Smuzhiyun static inline unsigned int mii_duplex (unsigned int duplex_lock,
196*4882a593Smuzhiyun unsigned int negotiated)
197*4882a593Smuzhiyun {
198*4882a593Smuzhiyun if (duplex_lock)
199*4882a593Smuzhiyun return 1;
200*4882a593Smuzhiyun if (mii_nway_result(negotiated) & LPA_DUPLEX)
201*4882a593Smuzhiyun return 1;
202*4882a593Smuzhiyun return 0;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun /**
206*4882a593Smuzhiyun * mii_resolve_flowctrl_fdx
207*4882a593Smuzhiyun * @lcladv: value of MII ADVERTISE register
208*4882a593Smuzhiyun * @rmtadv: value of MII LPA register
209*4882a593Smuzhiyun *
210*4882a593Smuzhiyun * Resolve full duplex flow control as per IEEE 802.3-2005 table 28B-3
211*4882a593Smuzhiyun */
mii_resolve_flowctrl_fdx(u16 lcladv,u16 rmtadv)212*4882a593Smuzhiyun static inline u8 mii_resolve_flowctrl_fdx(u16 lcladv, u16 rmtadv)
213*4882a593Smuzhiyun {
214*4882a593Smuzhiyun u8 cap = 0;
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun if (lcladv & rmtadv & ADVERTISE_PAUSE_CAP) {
217*4882a593Smuzhiyun cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
218*4882a593Smuzhiyun } else if (lcladv & rmtadv & ADVERTISE_PAUSE_ASYM) {
219*4882a593Smuzhiyun if (lcladv & ADVERTISE_PAUSE_CAP)
220*4882a593Smuzhiyun cap = FLOW_CTRL_RX;
221*4882a593Smuzhiyun else if (rmtadv & ADVERTISE_PAUSE_CAP)
222*4882a593Smuzhiyun cap = FLOW_CTRL_TX;
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun return cap;
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun #endif /* __LINUX_MII_H__ */
229