1*4882a593Smuzhiyun /* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM 2*4882a593Smuzhiyun * Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993 3*4882a593Smuzhiyun * derived from Data Sheet, Copyright Motorola 1984 (!). 4*4882a593Smuzhiyun * It was written to be part of the Linux operating system. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun /* permission is hereby granted to copy, modify and redistribute this code 7*4882a593Smuzhiyun * in terms of the GNU Library General Public License, Version 2 or later, 8*4882a593Smuzhiyun * at your option. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _MC146818RTC_H 12*4882a593Smuzhiyun #define _MC146818RTC_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <asm/io.h> 15*4882a593Smuzhiyun #include <linux/rtc.h> /* get the user-level API */ 16*4882a593Smuzhiyun #include <asm/mc146818rtc.h> /* register access macros */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /********************************************************************** 19*4882a593Smuzhiyun * register summary 20*4882a593Smuzhiyun **********************************************************************/ 21*4882a593Smuzhiyun #define RTC_SECONDS 0 22*4882a593Smuzhiyun #define RTC_SECONDS_ALARM 1 23*4882a593Smuzhiyun #define RTC_MINUTES 2 24*4882a593Smuzhiyun #define RTC_MINUTES_ALARM 3 25*4882a593Smuzhiyun #define RTC_HOURS 4 26*4882a593Smuzhiyun #define RTC_HOURS_ALARM 5 27*4882a593Smuzhiyun /* RTC_*_alarm is always true if 2 MSBs are set */ 28*4882a593Smuzhiyun # define RTC_ALARM_DONT_CARE 0xC0 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define RTC_DAY_OF_WEEK 6 31*4882a593Smuzhiyun #define RTC_DAY_OF_MONTH 7 32*4882a593Smuzhiyun #define RTC_MONTH 8 33*4882a593Smuzhiyun #define RTC_YEAR 9 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* control registers - Moto names 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun #define RTC_REG_A 10 38*4882a593Smuzhiyun #define RTC_REG_B 11 39*4882a593Smuzhiyun #define RTC_REG_C 12 40*4882a593Smuzhiyun #define RTC_REG_D 13 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /********************************************************************** 43*4882a593Smuzhiyun * register details 44*4882a593Smuzhiyun **********************************************************************/ 45*4882a593Smuzhiyun #define RTC_FREQ_SELECT RTC_REG_A 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus, 48*4882a593Smuzhiyun * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete, 49*4882a593Smuzhiyun * totalling to a max high interval of 2.228 ms. 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun # define RTC_UIP 0x80 52*4882a593Smuzhiyun # define RTC_DIV_CTL 0x70 53*4882a593Smuzhiyun /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */ 54*4882a593Smuzhiyun # define RTC_REF_CLCK_4MHZ 0x00 55*4882a593Smuzhiyun # define RTC_REF_CLCK_1MHZ 0x10 56*4882a593Smuzhiyun # define RTC_REF_CLCK_32KHZ 0x20 57*4882a593Smuzhiyun /* 2 values for divider stage reset, others for "testing purposes only" */ 58*4882a593Smuzhiyun # define RTC_DIV_RESET1 0x60 59*4882a593Smuzhiyun # define RTC_DIV_RESET2 0x70 60*4882a593Smuzhiyun /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */ 61*4882a593Smuzhiyun # define RTC_RATE_SELECT 0x0F 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /**********************************************************************/ 64*4882a593Smuzhiyun #define RTC_CONTROL RTC_REG_B 65*4882a593Smuzhiyun # define RTC_SET 0x80 /* disable updates for clock setting */ 66*4882a593Smuzhiyun # define RTC_PIE 0x40 /* periodic interrupt enable */ 67*4882a593Smuzhiyun # define RTC_AIE 0x20 /* alarm interrupt enable */ 68*4882a593Smuzhiyun # define RTC_UIE 0x10 /* update-finished interrupt enable */ 69*4882a593Smuzhiyun # define RTC_SQWE 0x08 /* enable square-wave output */ 70*4882a593Smuzhiyun # define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ 71*4882a593Smuzhiyun # define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ 72*4882a593Smuzhiyun # define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /**********************************************************************/ 75*4882a593Smuzhiyun #define RTC_INTR_FLAGS RTC_REG_C 76*4882a593Smuzhiyun /* caution - cleared by read */ 77*4882a593Smuzhiyun # define RTC_IRQF 0x80 /* any of the following 3 is active */ 78*4882a593Smuzhiyun # define RTC_PF 0x40 79*4882a593Smuzhiyun # define RTC_AF 0x20 80*4882a593Smuzhiyun # define RTC_UF 0x10 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /**********************************************************************/ 83*4882a593Smuzhiyun #define RTC_VALID RTC_REG_D 84*4882a593Smuzhiyun # define RTC_VRT 0x80 /* valid RAM and time */ 85*4882a593Smuzhiyun /**********************************************************************/ 86*4882a593Smuzhiyun #endif /* _MC146818RTC_H */ 87