1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Marvell MBUS common definitions. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2008 Marvell Semiconductor 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public 7*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any 8*4882a593Smuzhiyun * warranty of any kind, whether express or implied. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __LINUX_MBUS_H 12*4882a593Smuzhiyun #define __LINUX_MBUS_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct resource; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun struct mbus_dram_target_info { 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * The 4-bit MBUS target ID of the DRAM controller. 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun u8 mbus_dram_target_id; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * The base address, size, and MBUS attribute ID for each 24*4882a593Smuzhiyun * of the possible DRAM chip selects. Peripherals are 25*4882a593Smuzhiyun * required to support at least 4 decode windows. 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun int num_cs; 28*4882a593Smuzhiyun struct mbus_dram_window { 29*4882a593Smuzhiyun u8 cs_index; 30*4882a593Smuzhiyun u8 mbus_attr; 31*4882a593Smuzhiyun u32 base; 32*4882a593Smuzhiyun u32 size; 33*4882a593Smuzhiyun } cs[4]; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun struct mvebu_mbus_state { 37*4882a593Smuzhiyun void __iomem *mbuswins_base; 38*4882a593Smuzhiyun void __iomem *sdramwins_base; 39*4882a593Smuzhiyun struct dentry *debugfs_root; 40*4882a593Smuzhiyun struct dentry *debugfs_sdram; 41*4882a593Smuzhiyun struct dentry *debugfs_devs; 42*4882a593Smuzhiyun const struct mvebu_mbus_soc_data *soc; 43*4882a593Smuzhiyun int hw_io_coherency; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Flags for PCI/PCIe address decoding regions */ 47*4882a593Smuzhiyun #define MVEBU_MBUS_PCI_IO 0x1 48*4882a593Smuzhiyun #define MVEBU_MBUS_PCI_MEM 0x2 49*4882a593Smuzhiyun #define MVEBU_MBUS_PCI_WA 0x3 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * Magic value that explicits that we don't need a remapping-capable 53*4882a593Smuzhiyun * address decoding window. 54*4882a593Smuzhiyun */ 55*4882a593Smuzhiyun #define MVEBU_MBUS_NO_REMAP (0xffffffff) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* Maximum size of a mbus window name */ 58*4882a593Smuzhiyun #define MVEBU_MBUS_MAX_WINNAME_SZ 32 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun const struct mbus_dram_target_info *mvebu_mbus_dram_info(void); 61*4882a593Smuzhiyun void mvebu_mbus_get_pcie_mem_aperture(struct resource *res); 62*4882a593Smuzhiyun void mvebu_mbus_get_pcie_io_aperture(struct resource *res); 63*4882a593Smuzhiyun int mvebu_mbus_add_window_remap_by_id(unsigned int target, 64*4882a593Smuzhiyun unsigned int attribute, 65*4882a593Smuzhiyun phys_addr_t base, size_t size, 66*4882a593Smuzhiyun phys_addr_t remap); 67*4882a593Smuzhiyun int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute, 68*4882a593Smuzhiyun phys_addr_t base, size_t size); 69*4882a593Smuzhiyun int mvebu_mbus_del_window(phys_addr_t base, size_t size); 70*4882a593Smuzhiyun int mbus_dt_setup_win(struct mvebu_mbus_state *mbus, 71*4882a593Smuzhiyun u32 base, u32 size, u8 target, u8 attr); 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #endif /* __LINUX_MBUS_H */ 74