1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _ROCKCHIP_PLAT_IRQ_H_ 8*4882a593Smuzhiyun #define _ROCKCHIP_PLAT_IRQ_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #if defined(CONFIG_ROCKCHIP_RK3128) 11*4882a593Smuzhiyun #define GPIO0_PHYS 0x2007C000 12*4882a593Smuzhiyun #define GPIO1_PHYS 0x20080000 13*4882a593Smuzhiyun #define GPIO2_PHYS 0x20084000 14*4882a593Smuzhiyun #define GPIO3_PHYS 0x20088000 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define GIC_IRQS_NR (4 * 32) 17*4882a593Smuzhiyun #define GPIO_IRQS_NR (4 * 32) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define GPIO_BANK_NUM 4 20*4882a593Smuzhiyun #define GPIO_BANK_PINS 32 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define IRQ_USB_OTG 42 23*4882a593Smuzhiyun #define IRQ_TIMER1 61 24*4882a593Smuzhiyun #define IRQ_GPIO0 68 25*4882a593Smuzhiyun #define IRQ_GPIO1 69 26*4882a593Smuzhiyun #define IRQ_GPIO2 70 27*4882a593Smuzhiyun #define IRQ_GPIO3 71 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #elif defined(CONFIG_ROCKCHIP_RK322X) 30*4882a593Smuzhiyun #define GPIO0_PHYS 0x11110000 31*4882a593Smuzhiyun #define GPIO1_PHYS 0x11120000 32*4882a593Smuzhiyun #define GPIO2_PHYS 0x11130000 33*4882a593Smuzhiyun #define GPIO3_PHYS 0x11140000 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define GIC_IRQS_NR (4 * 32) 36*4882a593Smuzhiyun #define GPIO_IRQS_NR (4 * 32) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define GPIO_BANK_NUM 4 39*4882a593Smuzhiyun #define GPIO_BANK_PINS 32 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define IRQ_USB_OTG 55 42*4882a593Smuzhiyun #define IRQ_TIMER1 76 43*4882a593Smuzhiyun #define IRQ_PWM 82 44*4882a593Smuzhiyun #define IRQ_GPIO0 83 45*4882a593Smuzhiyun #define IRQ_GPIO1 84 46*4882a593Smuzhiyun #define IRQ_GPIO2 85 47*4882a593Smuzhiyun #define IRQ_GPIO3 86 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #elif defined(CONFIG_ROCKCHIP_RK3288) 50*4882a593Smuzhiyun #define GPIO0_PHYS 0xFF750000 51*4882a593Smuzhiyun #define GPIO1_PHYS 0xFF780000 52*4882a593Smuzhiyun #define GPIO2_PHYS 0xFF790000 53*4882a593Smuzhiyun #define GPIO3_PHYS 0xFF7A0000 54*4882a593Smuzhiyun #define GPIO4_PHYS 0xFF7B0000 55*4882a593Smuzhiyun #define GPIO5_PHYS 0xFF7C0000 56*4882a593Smuzhiyun #define GPIO6_PHYS 0xFF7D0000 57*4882a593Smuzhiyun #define GPIO7_PHYS 0xFF7E0000 58*4882a593Smuzhiyun #define GPIO8_PHYS 0xFF7F0000 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define GIC_IRQS_NR (5 * 32) 61*4882a593Smuzhiyun #define GPIO_IRQS_NR (9 * 32) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define GPIO_BANK_NUM 9 64*4882a593Smuzhiyun #define GPIO_BANK_PINS 32 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define IRQ_USB_OTG 55 67*4882a593Smuzhiyun #define IRQ_TIMER1 99 68*4882a593Smuzhiyun #define IRQ_PWM 110 69*4882a593Smuzhiyun #define IRQ_GPIO0 113 70*4882a593Smuzhiyun #define IRQ_GPIO1 114 71*4882a593Smuzhiyun #define IRQ_GPIO2 115 72*4882a593Smuzhiyun #define IRQ_GPIO3 116 73*4882a593Smuzhiyun #define IRQ_GPIO4 117 74*4882a593Smuzhiyun #define IRQ_GPIO5 118 75*4882a593Smuzhiyun #define IRQ_GPIO6 119 76*4882a593Smuzhiyun #define IRQ_GPIO7 120 77*4882a593Smuzhiyun #define IRQ_GPIO8 121 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #elif defined(CONFIG_ROCKCHIP_RK3328) 80*4882a593Smuzhiyun #define GPIO0_PHYS 0xFF210000 81*4882a593Smuzhiyun #define GPIO1_PHYS 0xFF220000 82*4882a593Smuzhiyun #define GPIO2_PHYS 0xFF230000 83*4882a593Smuzhiyun #define GPIO3_PHYS 0xFF240000 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define GIC_IRQS_NR (4 * 32) 86*4882a593Smuzhiyun #define GPIO_IRQS_NR (4 * 32) 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #define GPIO_BANK_NUM 4 89*4882a593Smuzhiyun #define GPIO_BANK_PINS 32 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define IRQ_TIMER1 76 92*4882a593Smuzhiyun #define IRQ_PWM 82 93*4882a593Smuzhiyun #define IRQ_GPIO0 83 94*4882a593Smuzhiyun #define IRQ_GPIO1 84 95*4882a593Smuzhiyun #define IRQ_GPIO2 85 96*4882a593Smuzhiyun #define IRQ_GPIO3 86 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #elif defined(CONFIG_ROCKCHIP_RK3368) 99*4882a593Smuzhiyun #define GPIO0_PHYS 0xFF750000 100*4882a593Smuzhiyun #define GPIO1_PHYS 0xFF780000 101*4882a593Smuzhiyun #define GPIO2_PHYS 0xFF790000 102*4882a593Smuzhiyun #define GPIO3_PHYS 0xFF7A0000 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define GIC_IRQS_NR (5 * 32) 105*4882a593Smuzhiyun #define GPIO_IRQS_NR (4 * 32) 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define GPIO_BANK_NUM 4 108*4882a593Smuzhiyun #define GPIO_BANK_PINS 32 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #define IRQ_TIMER0 98 111*4882a593Smuzhiyun #define IRQ_TIMER1 99 112*4882a593Smuzhiyun #define IRQ_PWM 110 113*4882a593Smuzhiyun #define IRQ_GPIO0 113 114*4882a593Smuzhiyun #define IRQ_GPIO1 114 115*4882a593Smuzhiyun #define IRQ_GPIO2 115 116*4882a593Smuzhiyun #define IRQ_GPIO3 116 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #elif defined(CONFIG_ROCKCHIP_RK3399) 119*4882a593Smuzhiyun #define GPIO0_PHYS 0xFF720000 120*4882a593Smuzhiyun #define GPIO1_PHYS 0xFF730000 121*4882a593Smuzhiyun #define GPIO2_PHYS 0xFF780000 122*4882a593Smuzhiyun #define GPIO3_PHYS 0xFF788000 123*4882a593Smuzhiyun #define GPIO4_PHYS 0xFF790000 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #define IRQ_GPIO0 46 126*4882a593Smuzhiyun #define IRQ_GPIO1 47 127*4882a593Smuzhiyun #define IRQ_GPIO2 48 128*4882a593Smuzhiyun #define IRQ_GPIO3 49 129*4882a593Smuzhiyun #define IRQ_GPIO4 50 130*4882a593Smuzhiyun #define IRQ_PWM 93 131*4882a593Smuzhiyun #define IRQ_TIMER1 114 /* non-secure */ 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #define GIC_IRQS_NR (6 * 32) 134*4882a593Smuzhiyun #define GPIO_IRQS_NR (5 * 32) 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #define GPIO_BANK_NUM 5 137*4882a593Smuzhiyun #define GPIO_BANK_PINS 32 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun #elif defined(CONFIG_ROCKCHIP_PX30) 140*4882a593Smuzhiyun #define GPIO0_PHYS 0xff040000 141*4882a593Smuzhiyun #define GPIO1_PHYS 0xff250000 142*4882a593Smuzhiyun #define GPIO2_PHYS 0xff260000 143*4882a593Smuzhiyun #define GPIO3_PHYS 0xff270000 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #define IRQ_GPIO0 35 146*4882a593Smuzhiyun #define IRQ_GPIO1 36 147*4882a593Smuzhiyun #define IRQ_GPIO2 37 148*4882a593Smuzhiyun #define IRQ_GPIO3 38 149*4882a593Smuzhiyun #define IRQ_PWM0 56 150*4882a593Smuzhiyun #define IRQ_PWM1 57 151*4882a593Smuzhiyun #define IRQ_TIMER0 62 /* non-secure */ 152*4882a593Smuzhiyun #define IRQ_TIMER1 63 /* non-secure */ 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun #define GIC_IRQS_NR (4 * 32) 155*4882a593Smuzhiyun #define GPIO_IRQS_NR (4 * 32) 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun #define GPIO_BANK_NUM 4 158*4882a593Smuzhiyun #define GPIO_BANK_PINS 32 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun #elif defined(CONFIG_ROCKCHIP_RK3308) 161*4882a593Smuzhiyun #define GPIO0_PHYS 0xff220000 162*4882a593Smuzhiyun #define GPIO1_PHYS 0xff230000 163*4882a593Smuzhiyun #define GPIO2_PHYS 0xff240000 164*4882a593Smuzhiyun #define GPIO3_PHYS 0xff250000 165*4882a593Smuzhiyun #define GPIO4_PHYS 0xff260000 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun #define IRQ_TIMER1 58 /* ch0 ns timer1 */ 168*4882a593Smuzhiyun #define IRQ_GPIO0 72 169*4882a593Smuzhiyun #define IRQ_GPIO1 73 170*4882a593Smuzhiyun #define IRQ_GPIO2 74 171*4882a593Smuzhiyun #define IRQ_GPIO3 75 172*4882a593Smuzhiyun #define IRQ_GPIO4 76 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun #define GIC_IRQS_NR (5 * 32) 175*4882a593Smuzhiyun #define GPIO_IRQS_NR (5 * 32) 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun #define GPIO_BANK_NUM 5 178*4882a593Smuzhiyun #define GPIO_BANK_PINS 32 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun #elif defined(CONFIG_ROCKCHIP_RK1808) 181*4882a593Smuzhiyun #define GPIO0_PHYS 0xff4c0000 182*4882a593Smuzhiyun #define GPIO1_PHYS 0xff690000 183*4882a593Smuzhiyun #define GPIO2_PHYS 0xff6a0000 184*4882a593Smuzhiyun #define GPIO3_PHYS 0xff6b0000 185*4882a593Smuzhiyun #define GPIO4_PHYS 0xff6c0000 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun #define IRQ_GPIO0 35 188*4882a593Smuzhiyun #define IRQ_GPIO1 36 189*4882a593Smuzhiyun #define IRQ_GPIO2 37 190*4882a593Smuzhiyun #define IRQ_GPIO3 38 191*4882a593Smuzhiyun #define IRQ_GPIO4 114 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun #define IRQ_TIMER0 58 194*4882a593Smuzhiyun #define IRQ_TIMER1 59 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun #define GIC_IRQS_NR (5 * 32) 197*4882a593Smuzhiyun #define GPIO_IRQS_NR (5 * 32) 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun #define GPIO_BANK_NUM 5 200*4882a593Smuzhiyun #define GPIO_BANK_PINS 32 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun #elif defined(CONFIG_ROCKCHIP_RV1106) 203*4882a593Smuzhiyun #define GPIO0_PHYS 0xff460000 204*4882a593Smuzhiyun #define GPIO1_PHYS 0xff620000 205*4882a593Smuzhiyun #define GPIO2_PHYS 0xff630000 206*4882a593Smuzhiyun #define GPIO3_PHYS 0xff640000 207*4882a593Smuzhiyun #define GPIO4_PHYS 0xff650000 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun #define GIC_IRQS_NR (5 * 32) 210*4882a593Smuzhiyun #define GPIO_IRQS_NR (5 * 32) 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun #define GPIO_BANK_NUM 5 213*4882a593Smuzhiyun #define GPIO_BANK_PINS 32 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun #define IRQ_USB_OTG 117 216*4882a593Smuzhiyun #define IRQ_TIMER1 57 217*4882a593Smuzhiyun #define IRQ_GPIO0 66 218*4882a593Smuzhiyun #define IRQ_GPIO1 67 219*4882a593Smuzhiyun #define IRQ_GPIO2 68 220*4882a593Smuzhiyun #define IRQ_GPIO3 69 221*4882a593Smuzhiyun #define IRQ_GPIO4 70 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun #elif defined(CONFIG_ROCKCHIP_RV1126) 224*4882a593Smuzhiyun #define GPIO0_PHYS 0xff460000 225*4882a593Smuzhiyun #define GPIO1_PHYS 0xff620000 226*4882a593Smuzhiyun #define GPIO2_PHYS 0xff630000 227*4882a593Smuzhiyun #define GPIO3_PHYS 0xff640000 228*4882a593Smuzhiyun #define GPIO4_PHYS 0xff650000 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun #define GIC_IRQS_NR (5 * 32) 231*4882a593Smuzhiyun #define GPIO_IRQS_NR (5 * 32) 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun #define GPIO_BANK_NUM 5 234*4882a593Smuzhiyun #define GPIO_BANK_PINS 32 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun #define IRQ_USB_OTG 117 237*4882a593Smuzhiyun #define IRQ_TIMER1 57 238*4882a593Smuzhiyun #define IRQ_GPIO0 66 239*4882a593Smuzhiyun #define IRQ_GPIO1 67 240*4882a593Smuzhiyun #define IRQ_GPIO2 68 241*4882a593Smuzhiyun #define IRQ_GPIO3 69 242*4882a593Smuzhiyun #define IRQ_GPIO4 70 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun #elif defined(CONFIG_ROCKCHIP_RK3528) 245*4882a593Smuzhiyun #define GPIO0_PHYS 0xff610000 246*4882a593Smuzhiyun #define GPIO1_PHYS 0xffaf0000 247*4882a593Smuzhiyun #define GPIO2_PHYS 0xffb00000 248*4882a593Smuzhiyun #define GPIO3_PHYS 0xffb10000 249*4882a593Smuzhiyun #define GPIO4_PHYS 0xffb20000 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun #define GIC_IRQS_NR (5 * 32) 252*4882a593Smuzhiyun #define GPIO_IRQS_NR (5 * 32) 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun #define GPIO_BANK_NUM 5 255*4882a593Smuzhiyun #define GPIO_BANK_PINS 32 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun #define IRQ_TIMER0 63 258*4882a593Smuzhiyun #define IRQ_GPIO0 103 259*4882a593Smuzhiyun #define IRQ_GPIO1 105 260*4882a593Smuzhiyun #define IRQ_GPIO2 107 261*4882a593Smuzhiyun #define IRQ_GPIO3 108 262*4882a593Smuzhiyun #define IRQ_GPIO4 110 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun #elif defined(CONFIG_ROCKCHIP_RK3562) 265*4882a593Smuzhiyun #define GPIO0_PHYS 0xff260000 266*4882a593Smuzhiyun #define GPIO1_PHYS 0xff620000 267*4882a593Smuzhiyun #define GPIO2_PHYS 0xff630000 268*4882a593Smuzhiyun #define GPIO3_PHYS 0xffac0000 269*4882a593Smuzhiyun #define GPIO4_PHYS 0xffad0000 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun #define GIC_IRQS_NR (5 * 32) 272*4882a593Smuzhiyun #define GPIO_IRQS_NR (5 * 32) 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun #define GPIO_BANK_NUM 5 275*4882a593Smuzhiyun #define GPIO_BANK_PINS 32 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun #define IRQ_TIMER0 77 278*4882a593Smuzhiyun #define IRQ_GPIO0 32 279*4882a593Smuzhiyun #define IRQ_GPIO1 34 280*4882a593Smuzhiyun #define IRQ_GPIO2 36 281*4882a593Smuzhiyun #define IRQ_GPIO3 38 282*4882a593Smuzhiyun #define IRQ_GPIO4 40 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun #elif defined(CONFIG_ROCKCHIP_RK3568) 285*4882a593Smuzhiyun #define GPIO0_PHYS 0xfdd60000 286*4882a593Smuzhiyun #define GPIO1_PHYS 0xfe740000 287*4882a593Smuzhiyun #define GPIO2_PHYS 0xfe750000 288*4882a593Smuzhiyun #define GPIO3_PHYS 0xfe760000 289*4882a593Smuzhiyun #define GPIO4_PHYS 0xfe770000 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun #define GIC_IRQS_NR (5 * 32) 292*4882a593Smuzhiyun #define GPIO_IRQS_NR (5 * 32) 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun #define GPIO_BANK_NUM 5 295*4882a593Smuzhiyun #define GPIO_BANK_PINS 32 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun #define IRQ_TIMER0 141 298*4882a593Smuzhiyun #define IRQ_GPIO0 65 299*4882a593Smuzhiyun #define IRQ_GPIO1 66 300*4882a593Smuzhiyun #define IRQ_GPIO2 67 301*4882a593Smuzhiyun #define IRQ_GPIO3 68 302*4882a593Smuzhiyun #define IRQ_GPIO4 69 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun #elif defined(CONFIG_ROCKCHIP_RK3588) 305*4882a593Smuzhiyun #define GPIO0_PHYS 0xfd8a0000 306*4882a593Smuzhiyun #define GPIO1_PHYS 0xfec20000 307*4882a593Smuzhiyun #define GPIO2_PHYS 0xfec30000 308*4882a593Smuzhiyun #define GPIO3_PHYS 0xfec40000 309*4882a593Smuzhiyun #define GPIO4_PHYS 0xfec50000 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun #define GIC_IRQS_NR (455) 312*4882a593Smuzhiyun #define GPIO_IRQS_NR (5 * 32) 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun #define GPIO_BANK_NUM 5 315*4882a593Smuzhiyun #define GPIO_BANK_PINS 32 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun #define IRQ_TIMER0 321 318*4882a593Smuzhiyun #define IRQ_GPIO0 309 319*4882a593Smuzhiyun #define IRQ_GPIO1 310 320*4882a593Smuzhiyun #define IRQ_GPIO2 311 321*4882a593Smuzhiyun #define IRQ_GPIO3 312 322*4882a593Smuzhiyun #define IRQ_GPIO4 313 323*4882a593Smuzhiyun #else 324*4882a593Smuzhiyun "Missing define RIQ relative things" 325*4882a593Smuzhiyun #endif 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun #endif /* _ROCKCHIP_PLAT_IRQ_H_ */ 328