1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * definitions for MPC8xxx I/O Ports 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Murray.Jensen@cmst.csiro.au, 20-Oct-00 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* 8*4882a593Smuzhiyun * this structure mirrors the layout of the five port registers in 9*4882a593Smuzhiyun * the internal memory map 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun typedef struct { 12*4882a593Smuzhiyun unsigned int pdir; /* Port Data Direction Register (35-3) */ 13*4882a593Smuzhiyun unsigned int ppar; /* Port Pin Assignment Register (35-4) */ 14*4882a593Smuzhiyun unsigned int psor; /* Port Special Options Register (35-5) */ 15*4882a593Smuzhiyun unsigned int podr; /* Port Open Drain Register (35-2) */ 16*4882a593Smuzhiyun unsigned int pdat; /* Port Data Register (35-3) */ 17*4882a593Smuzhiyun } ioport_t; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun * this macro calculates the address within the internal 21*4882a593Smuzhiyun * memory map (im) of the set of registers for a port (idx) 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * the internal memory map aligns the above structure on 24*4882a593Smuzhiyun * a 0x20 byte boundary 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun #ifdef CONFIG_MPC85xx 27*4882a593Smuzhiyun #define ioport_addr(im, idx) (ioport_t *)((uint)&(im->im_cpm_iop) + ((idx)*0x20)) 28*4882a593Smuzhiyun #else 29*4882a593Smuzhiyun #define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20)) 30*4882a593Smuzhiyun #endif 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* 33*4882a593Smuzhiyun * this structure provides configuration 34*4882a593Smuzhiyun * information for one port pin 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun typedef struct { 37*4882a593Smuzhiyun unsigned char conf:1; /* if 1, configure this port */ 38*4882a593Smuzhiyun unsigned char ppar:1; /* Port Pin Assignment Register (35-4) */ 39*4882a593Smuzhiyun unsigned char psor:1; /* Port Special Options Register (35-2) */ 40*4882a593Smuzhiyun unsigned char pdir:1; /* Port Data Direction Register (35-3) */ 41*4882a593Smuzhiyun unsigned char podr:1; /* Port Open Drain Register (35-2) */ 42*4882a593Smuzhiyun unsigned char pdat:1; /* Port Data Register (35-2) */ 43*4882a593Smuzhiyun } iop_conf_t; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* 46*4882a593Smuzhiyun * a table that contains configuration information for all 32 pins 47*4882a593Smuzhiyun * 48*4882a593Smuzhiyun * NOTE: in the second dimension of this table, index 0 refers to pin 31 49*4882a593Smuzhiyun * and index 31 refers to pin 0. this made the code in the table look more 50*4882a593Smuzhiyun * like the table in the 8260UM (and in the hymod manuals). 51*4882a593Smuzhiyun */ 52*4882a593Smuzhiyun extern const iop_conf_t iop_conf_tab[4][32]; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun typedef struct { 55*4882a593Smuzhiyun unsigned char port; 56*4882a593Smuzhiyun unsigned char pin; 57*4882a593Smuzhiyun int dir; 58*4882a593Smuzhiyun int open_drain; 59*4882a593Smuzhiyun int assign; 60*4882a593Smuzhiyun } qe_iop_conf_t; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define QE_IOP_TAB_END (-1) 63