1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2012 Samsung Electronics 3*4882a593Smuzhiyun * R. Chandrasekar <rcsekar@samsung.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __I2S_H__ 9*4882a593Smuzhiyun #define __I2S_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * DAI hardware audio formats. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * Describes the physical PCM data formating and clocking. Add new formats 15*4882a593Smuzhiyun * to the end. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun #define SND_SOC_DAIFMT_I2S 1 /* I2S mode */ 18*4882a593Smuzhiyun #define SND_SOC_DAIFMT_RIGHT_J 2 /* Right Justified mode */ 19*4882a593Smuzhiyun #define SND_SOC_DAIFMT_LEFT_J 3 /* Left Justified mode */ 20*4882a593Smuzhiyun #define SND_SOC_DAIFMT_DSP_A 4 /* L data MSB after FRM LRC */ 21*4882a593Smuzhiyun #define SND_SOC_DAIFMT_DSP_B 5 /* L data MSB during FRM LRC */ 22*4882a593Smuzhiyun #define SND_SOC_DAIFMT_AC97 6 /* AC97 */ 23*4882a593Smuzhiyun #define SND_SOC_DAIFMT_PDM 7 /* Pulse density modulation */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* left and right justified also known as MSB and LSB respectively */ 26*4882a593Smuzhiyun #define SND_SOC_DAIFMT_MSB SND_SOC_DAIFMT_LEFT_J 27*4882a593Smuzhiyun #define SND_SOC_DAIFMT_LSB SND_SOC_DAIFMT_RIGHT_J 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * DAI hardware signal inversions. 31*4882a593Smuzhiyun * 32*4882a593Smuzhiyun * Specifies whether the DAI can also support inverted clocks for the specified 33*4882a593Smuzhiyun * format. 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun #define SND_SOC_DAIFMT_NB_NF (1 << 8) /* normal bit clock + frame */ 36*4882a593Smuzhiyun #define SND_SOC_DAIFMT_NB_IF (2 << 8) /* normal BCLK + inv FRM */ 37*4882a593Smuzhiyun #define SND_SOC_DAIFMT_IB_NF (3 << 8) /* invert BCLK + nor FRM */ 38*4882a593Smuzhiyun #define SND_SOC_DAIFMT_IB_IF (4 << 8) /* invert BCLK + FRM */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* 41*4882a593Smuzhiyun * DAI hardware clock masters. 42*4882a593Smuzhiyun * 43*4882a593Smuzhiyun * This is wrt the codec, the inverse is true for the interface 44*4882a593Smuzhiyun * i.e. if the codec is clk and FRM master then the interface is 45*4882a593Smuzhiyun * clk and frame slave. 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun #define SND_SOC_DAIFMT_CBM_CFM (1 << 12) /* codec clk & FRM master */ 48*4882a593Smuzhiyun #define SND_SOC_DAIFMT_CBS_CFM (2 << 12) /* codec clk slave & FRM master */ 49*4882a593Smuzhiyun #define SND_SOC_DAIFMT_CBM_CFS (3 << 12) /* codec clk master & frame slave */ 50*4882a593Smuzhiyun #define SND_SOC_DAIFMT_CBS_CFS (4 << 12) /* codec clk & FRM slave */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define SND_SOC_DAIFMT_FORMAT_MASK 0x000f 53*4882a593Smuzhiyun #define SND_SOC_DAIFMT_CLOCK_MASK 0x00f0 54*4882a593Smuzhiyun #define SND_SOC_DAIFMT_INV_MASK 0x0f00 55*4882a593Smuzhiyun #define SND_SOC_DAIFMT_MASTER_MASK 0xf000 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* 58*4882a593Smuzhiyun * Master Clock Directions 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun #define SND_SOC_CLOCK_IN 0 61*4882a593Smuzhiyun #define SND_SOC_CLOCK_OUT 1 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* I2S Tx Control */ 64*4882a593Smuzhiyun #define I2S_TX_ON 1 65*4882a593Smuzhiyun #define I2S_TX_OFF 0 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define FIFO_LENGTH 64 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* I2s Registers */ 70*4882a593Smuzhiyun struct i2s_reg { 71*4882a593Smuzhiyun unsigned int con; /* base + 0 , Control register */ 72*4882a593Smuzhiyun unsigned int mod; /* Mode register */ 73*4882a593Smuzhiyun unsigned int fic; /* FIFO control register */ 74*4882a593Smuzhiyun unsigned int psr; /* Reserved */ 75*4882a593Smuzhiyun unsigned int txd; /* Transmit data register */ 76*4882a593Smuzhiyun unsigned int rxd; /* Receive Data Register */ 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* This structure stores the i2s related information */ 80*4882a593Smuzhiyun struct i2stx_info { 81*4882a593Smuzhiyun unsigned int rfs; /* LR clock frame size */ 82*4882a593Smuzhiyun unsigned int bfs; /* Bit slock frame size */ 83*4882a593Smuzhiyun unsigned int audio_pll_clk; /* Audio pll frequency in Hz */ 84*4882a593Smuzhiyun unsigned int samplingrate; /* sampling rate */ 85*4882a593Smuzhiyun unsigned int bitspersample; /* bits per sample */ 86*4882a593Smuzhiyun unsigned int channels; /* audio channels */ 87*4882a593Smuzhiyun unsigned int base_address; /* I2S Register Base */ 88*4882a593Smuzhiyun unsigned int id; /* I2S controller id */ 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* 92*4882a593Smuzhiyun * Sends the given data through i2s tx 93*4882a593Smuzhiyun * 94*4882a593Smuzhiyun * @param pi2s_tx pointer of i2s transmitter parameter structure. 95*4882a593Smuzhiyun * @param data address of the data buffer 96*4882a593Smuzhiyun * @param data_size array size of the int buffer (total size / size of int) 97*4882a593Smuzhiyun * 98*4882a593Smuzhiyun * @return int value 0 for success, -1 in case of error 99*4882a593Smuzhiyun */ 100*4882a593Smuzhiyun int i2s_transfer_tx_data(struct i2stx_info *pi2s_tx, unsigned *data, 101*4882a593Smuzhiyun unsigned long data_size); 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* 104*4882a593Smuzhiyun * Initialise i2s transmiter 105*4882a593Smuzhiyun * 106*4882a593Smuzhiyun * @param pi2s_tx pointer of i2s transmitter parameter structure. 107*4882a593Smuzhiyun * 108*4882a593Smuzhiyun * @return int value 0 for success, -1 in case of error 109*4882a593Smuzhiyun */ 110*4882a593Smuzhiyun int i2s_tx_init(struct i2stx_info *pi2s_tx); 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #endif /* __I2S_H__ */ 113