1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2021 Rockchip Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __PHY_PCIE_H_ 7*4882a593Smuzhiyun #define __PHY_PCIE_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /** 10*4882a593Smuzhiyun * struct phy_configure_opts_pcie - PCIe PHY configuration set 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * This structure is used to represent the configuration state of a 13*4882a593Smuzhiyun * PCIe phy. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun struct phy_configure_opts_pcie { 16*4882a593Smuzhiyun bool is_bifurcation; /* Bifurcation mode support */ 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #endif /* __PHY_PCIE_H_ */ 20