1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Freescale USB Controller 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _ASM_FSL_USB_H_ 10*4882a593Smuzhiyun #define _ASM_FSL_USB_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 13*4882a593Smuzhiyun struct ccsr_usb_port_ctrl { 14*4882a593Smuzhiyun u32 ctrl; 15*4882a593Smuzhiyun u32 drvvbuscfg; 16*4882a593Smuzhiyun u32 pwrfltcfg; 17*4882a593Smuzhiyun u32 sts; 18*4882a593Smuzhiyun u8 res_14[0xc]; 19*4882a593Smuzhiyun u32 bistcfg; 20*4882a593Smuzhiyun u32 biststs; 21*4882a593Smuzhiyun u32 abistcfg; 22*4882a593Smuzhiyun u32 abiststs; 23*4882a593Smuzhiyun u8 res_30[0x10]; 24*4882a593Smuzhiyun u32 xcvrprg; 25*4882a593Smuzhiyun u32 anaprg; 26*4882a593Smuzhiyun u32 anadrv; 27*4882a593Smuzhiyun u32 anasts; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun struct ccsr_usb_phy { 31*4882a593Smuzhiyun u32 id; 32*4882a593Smuzhiyun struct ccsr_usb_port_ctrl port1; 33*4882a593Smuzhiyun u8 res_50[0xc]; 34*4882a593Smuzhiyun u32 tvr; 35*4882a593Smuzhiyun u32 pllprg[4]; 36*4882a593Smuzhiyun u8 res_70[0x4]; 37*4882a593Smuzhiyun u32 anaccfg; 38*4882a593Smuzhiyun u32 dbg; 39*4882a593Smuzhiyun u8 res_7c[0x4]; 40*4882a593Smuzhiyun struct ccsr_usb_port_ctrl port2; 41*4882a593Smuzhiyun u8 res_dc[0x334]; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0) 45*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1) 46*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1) 47*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV (1 << 0) 48*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0) 49*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1) 50*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13) 51*4882a593Smuzhiyun #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 52*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK (5 << 4) 53*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK (6 << 16) 54*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN (1 << 20) 55*4882a593Smuzhiyun #endif 56*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4) 57*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16) 58*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21) 59*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0) 60*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7) 61*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define INC_DCNT_THRESHOLD_25MV (0 << 4) 64*4882a593Smuzhiyun #define INC_DCNT_THRESHOLD_50MV (1 << 4) 65*4882a593Smuzhiyun #define DEC_DCNT_THRESHOLD_25MV (2 << 4) 66*4882a593Smuzhiyun #define DEC_DCNT_THRESHOLD_50MV (3 << 4) 67*4882a593Smuzhiyun #else 68*4882a593Smuzhiyun struct ccsr_usb_phy { 69*4882a593Smuzhiyun u32 config1; 70*4882a593Smuzhiyun u32 config2; 71*4882a593Smuzhiyun u32 config3; 72*4882a593Smuzhiyun u32 config4; 73*4882a593Smuzhiyun u32 config5; 74*4882a593Smuzhiyun u32 status1; 75*4882a593Smuzhiyun u32 usb_enable_override; 76*4882a593Smuzhiyun u8 res[0xe4]; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USB_HS_DISCNCT_INC (3 << 22) 79*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL (1 << 20) 80*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0 13 81*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3 16 82*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0 0 83*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3 3 84*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1 85*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07 86*4882a593Smuzhiyun #endif 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* USB Erratum Checking code */ 89*4882a593Smuzhiyun #if defined(CONFIG_PPC) || defined(CONFIG_ARM) 90*4882a593Smuzhiyun bool has_dual_phy(void); 91*4882a593Smuzhiyun bool has_erratum_a006261(void); 92*4882a593Smuzhiyun bool has_erratum_a007075(void); 93*4882a593Smuzhiyun bool has_erratum_a007798(void); 94*4882a593Smuzhiyun bool has_erratum_a007792(void); 95*4882a593Smuzhiyun bool has_erratum_a005697(void); 96*4882a593Smuzhiyun bool has_erratum_a004477(void); 97*4882a593Smuzhiyun bool has_erratum_a008751(void); 98*4882a593Smuzhiyun bool has_erratum_a010151(void); 99*4882a593Smuzhiyun #endif 100*4882a593Smuzhiyun #endif /*_ASM_FSL_USB_H_ */ 101