1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010 3*4882a593Smuzhiyun * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * (C) Copyright 2009 Freescale Semiconductor, Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __FSL_PMIC_H__ 11*4882a593Smuzhiyun #define __FSL_PMIC_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * The registers of different PMIC has the same meaning 15*4882a593Smuzhiyun * but the bit positions of the fields can differ or 16*4882a593Smuzhiyun * some fields has a meaning only on some devices. 17*4882a593Smuzhiyun * You have to check with the internal SPI bitmap 18*4882a593Smuzhiyun * (see Freescale Documentation) to set the registers 19*4882a593Smuzhiyun * for the device you are using 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun enum { 22*4882a593Smuzhiyun REG_INT_STATUS0 = 0, 23*4882a593Smuzhiyun REG_INT_MASK0, 24*4882a593Smuzhiyun REG_INT_SENSE0, 25*4882a593Smuzhiyun REG_INT_STATUS1, 26*4882a593Smuzhiyun REG_INT_MASK1, 27*4882a593Smuzhiyun REG_INT_SENSE1, 28*4882a593Smuzhiyun REG_PU_MODE_S, 29*4882a593Smuzhiyun REG_IDENTIFICATION, 30*4882a593Smuzhiyun REG_UNUSED0, 31*4882a593Smuzhiyun REG_ACC0, 32*4882a593Smuzhiyun REG_ACC1, /*10 */ 33*4882a593Smuzhiyun REG_UNUSED1, 34*4882a593Smuzhiyun REG_UNUSED2, 35*4882a593Smuzhiyun REG_POWER_CTL0, 36*4882a593Smuzhiyun REG_POWER_CTL1, 37*4882a593Smuzhiyun REG_POWER_CTL2, 38*4882a593Smuzhiyun REG_REGEN_ASSIGN, 39*4882a593Smuzhiyun REG_UNUSED3, 40*4882a593Smuzhiyun REG_MEM_A, 41*4882a593Smuzhiyun REG_MEM_B, 42*4882a593Smuzhiyun REG_RTC_TIME, /*20 */ 43*4882a593Smuzhiyun REG_RTC_ALARM, 44*4882a593Smuzhiyun REG_RTC_DAY, 45*4882a593Smuzhiyun REG_RTC_DAY_ALARM, 46*4882a593Smuzhiyun REG_SW_0, 47*4882a593Smuzhiyun REG_SW_1, 48*4882a593Smuzhiyun REG_SW_2, 49*4882a593Smuzhiyun REG_SW_3, 50*4882a593Smuzhiyun REG_SW_4, 51*4882a593Smuzhiyun REG_SW_5, 52*4882a593Smuzhiyun REG_SETTING_0, /*30 */ 53*4882a593Smuzhiyun REG_SETTING_1, 54*4882a593Smuzhiyun REG_MODE_0, 55*4882a593Smuzhiyun REG_MODE_1, 56*4882a593Smuzhiyun REG_POWER_MISC, 57*4882a593Smuzhiyun REG_UNUSED4, 58*4882a593Smuzhiyun REG_UNUSED5, 59*4882a593Smuzhiyun REG_UNUSED6, 60*4882a593Smuzhiyun REG_UNUSED7, 61*4882a593Smuzhiyun REG_UNUSED8, 62*4882a593Smuzhiyun REG_UNUSED9, /*40 */ 63*4882a593Smuzhiyun REG_UNUSED10, 64*4882a593Smuzhiyun REG_UNUSED11, 65*4882a593Smuzhiyun REG_ADC0, 66*4882a593Smuzhiyun REG_ADC1, 67*4882a593Smuzhiyun REG_ADC2, 68*4882a593Smuzhiyun REG_ADC3, 69*4882a593Smuzhiyun REG_ADC4, 70*4882a593Smuzhiyun REG_CHARGE, 71*4882a593Smuzhiyun REG_USB0, 72*4882a593Smuzhiyun REG_USB1, /*50 */ 73*4882a593Smuzhiyun REG_LED_CTL0, 74*4882a593Smuzhiyun REG_LED_CTL1, 75*4882a593Smuzhiyun REG_LED_CTL2, 76*4882a593Smuzhiyun REG_LED_CTL3, 77*4882a593Smuzhiyun REG_UNUSED12, 78*4882a593Smuzhiyun REG_UNUSED13, 79*4882a593Smuzhiyun REG_TRIM0, 80*4882a593Smuzhiyun REG_TRIM1, 81*4882a593Smuzhiyun REG_TEST0, 82*4882a593Smuzhiyun REG_TEST1, /*60 */ 83*4882a593Smuzhiyun REG_TEST2, 84*4882a593Smuzhiyun REG_TEST3, 85*4882a593Smuzhiyun REG_TEST4, 86*4882a593Smuzhiyun PMIC_NUM_OF_REGS, 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* REG_POWER_MISC */ 90*4882a593Smuzhiyun #define GPO1EN (1 << 6) 91*4882a593Smuzhiyun #define GPO1STBY (1 << 7) 92*4882a593Smuzhiyun #define GPO2EN (1 << 8) 93*4882a593Smuzhiyun #define GPO2STBY (1 << 9) 94*4882a593Smuzhiyun #define GPO3EN (1 << 10) 95*4882a593Smuzhiyun #define GPO3STBY (1 << 11) 96*4882a593Smuzhiyun #define GPO4EN (1 << 12) 97*4882a593Smuzhiyun #define GPO4STBY (1 << 13) 98*4882a593Smuzhiyun #define PWGT1SPIEN (1 << 15) 99*4882a593Smuzhiyun #define PWGT2SPIEN (1 << 16) 100*4882a593Smuzhiyun #define PWUP (1 << 21) 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* Power Control 0 */ 103*4882a593Smuzhiyun #define COINCHEN (1 << 23) 104*4882a593Smuzhiyun #define BATTDETEN (1 << 19) 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* Interrupt status 1 */ 107*4882a593Smuzhiyun #define RTCRSTI (1 << 7) 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* MC34708 Definitions */ 110*4882a593Smuzhiyun #define SWx_VOLT_MASK_MC34708 0x3F 111*4882a593Smuzhiyun #define SWx_1_250V_MC34708 0x30 112*4882a593Smuzhiyun #define SWx_1_300V_MC34708 0x34 113*4882a593Smuzhiyun #define TIMER_MASK_MC34708 0x300 114*4882a593Smuzhiyun #define TIMER_4S_MC34708 0x100 115*4882a593Smuzhiyun #define VUSBSEL_MC34708 (1 << 2) 116*4882a593Smuzhiyun #define VUSBEN_MC34708 (1 << 3) 117*4882a593Smuzhiyun #define SWBST_CTRL 31 118*4882a593Smuzhiyun #define SWBST_AUTO 0x8 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #endif 121