1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2009-2012, 2013 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * Jun-jie Zhang <b18070@freescale.com> 4*4882a593Smuzhiyun * Mingkai Hu <Mingkai.hu@freescale.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __FSL_PHY_H__ 10*4882a593Smuzhiyun #define __FSL_PHY_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <net.h> 13*4882a593Smuzhiyun #include <miiphy.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct tsec_mii_mng { 16*4882a593Smuzhiyun u32 miimcfg; /* MII management configuration reg */ 17*4882a593Smuzhiyun u32 miimcom; /* MII management command reg */ 18*4882a593Smuzhiyun u32 miimadd; /* MII management address reg */ 19*4882a593Smuzhiyun u32 miimcon; /* MII management control reg */ 20*4882a593Smuzhiyun u32 miimstat; /* MII management status reg */ 21*4882a593Smuzhiyun u32 miimind; /* MII management indication reg */ 22*4882a593Smuzhiyun u32 ifstat; /* Interface Status Register */ 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc); 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* PHY register offsets */ 28*4882a593Smuzhiyun #define PHY_EXT_PAGE_ACCESS 0x1f 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* MII Management Configuration Register */ 31*4882a593Smuzhiyun #define MIIMCFG_RESET_MGMT 0x80000000 32*4882a593Smuzhiyun #define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007 33*4882a593Smuzhiyun #define MIIMCFG_INIT_VALUE 0x00000003 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* MII Management Command Register */ 36*4882a593Smuzhiyun #define MIIMCOM_READ_CYCLE 0x00000001 37*4882a593Smuzhiyun #define MIIMCOM_SCAN_CYCLE 0x00000002 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* MII Management Address Register */ 40*4882a593Smuzhiyun #define MIIMADD_PHY_ADDR_SHIFT 8 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* MII Management Indicator Register */ 43*4882a593Smuzhiyun #define MIIMIND_BUSY 0x00000001 44*4882a593Smuzhiyun #define MIIMIND_NOTVALID 0x00000004 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr, 47*4882a593Smuzhiyun int dev_addr, int reg, int value); 48*4882a593Smuzhiyun int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr, 49*4882a593Smuzhiyun int dev_addr, int regnum); 50*4882a593Smuzhiyun int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum); 51*4882a593Smuzhiyun int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum, 52*4882a593Smuzhiyun u16 value); 53*4882a593Smuzhiyun int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, 54*4882a593Smuzhiyun int regnum, u16 value); 55*4882a593Smuzhiyun int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, 56*4882a593Smuzhiyun int regnum); 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun struct fsl_pq_mdio_info { 59*4882a593Smuzhiyun struct tsec_mii_mng __iomem *regs; 60*4882a593Smuzhiyun char *name; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info); 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #endif /* __FSL_PHY_H__ */ 65