1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Common internal memory map for some Freescale SoCs 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2013-2014 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __FSL_IMMAP_H 10*4882a593Smuzhiyun #define __FSL_IMMAP_H 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * DDR memory controller registers 13*4882a593Smuzhiyun * This structure works for mpc83xx (DDR2 and DDR3), mpc85xx, mpc86xx. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun struct ccsr_ddr { 16*4882a593Smuzhiyun u32 cs0_bnds; /* Chip Select 0 Memory Bounds */ 17*4882a593Smuzhiyun u8 res_04[4]; 18*4882a593Smuzhiyun u32 cs1_bnds; /* Chip Select 1 Memory Bounds */ 19*4882a593Smuzhiyun u8 res_0c[4]; 20*4882a593Smuzhiyun u32 cs2_bnds; /* Chip Select 2 Memory Bounds */ 21*4882a593Smuzhiyun u8 res_14[4]; 22*4882a593Smuzhiyun u32 cs3_bnds; /* Chip Select 3 Memory Bounds */ 23*4882a593Smuzhiyun u8 res_1c[100]; 24*4882a593Smuzhiyun u32 cs0_config; /* Chip Select Configuration */ 25*4882a593Smuzhiyun u32 cs1_config; /* Chip Select Configuration */ 26*4882a593Smuzhiyun u32 cs2_config; /* Chip Select Configuration */ 27*4882a593Smuzhiyun u32 cs3_config; /* Chip Select Configuration */ 28*4882a593Smuzhiyun u8 res_90[48]; 29*4882a593Smuzhiyun u32 cs0_config_2; /* Chip Select Configuration 2 */ 30*4882a593Smuzhiyun u32 cs1_config_2; /* Chip Select Configuration 2 */ 31*4882a593Smuzhiyun u32 cs2_config_2; /* Chip Select Configuration 2 */ 32*4882a593Smuzhiyun u32 cs3_config_2; /* Chip Select Configuration 2 */ 33*4882a593Smuzhiyun u8 res_d0[48]; 34*4882a593Smuzhiyun u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ 35*4882a593Smuzhiyun u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ 36*4882a593Smuzhiyun u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ 37*4882a593Smuzhiyun u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ 38*4882a593Smuzhiyun u32 sdram_cfg; /* SDRAM Control Configuration */ 39*4882a593Smuzhiyun u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */ 40*4882a593Smuzhiyun u32 sdram_mode; /* SDRAM Mode Configuration */ 41*4882a593Smuzhiyun u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */ 42*4882a593Smuzhiyun u32 sdram_md_cntl; /* SDRAM Mode Control */ 43*4882a593Smuzhiyun u32 sdram_interval; /* SDRAM Interval Configuration */ 44*4882a593Smuzhiyun u32 sdram_data_init; /* SDRAM Data initialization */ 45*4882a593Smuzhiyun u8 res_12c[4]; 46*4882a593Smuzhiyun u32 sdram_clk_cntl; /* SDRAM Clock Control */ 47*4882a593Smuzhiyun u8 res_134[20]; 48*4882a593Smuzhiyun u32 init_addr; /* training init addr */ 49*4882a593Smuzhiyun u32 init_ext_addr; /* training init extended addr */ 50*4882a593Smuzhiyun u8 res_150[16]; 51*4882a593Smuzhiyun u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ 52*4882a593Smuzhiyun u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ 53*4882a593Smuzhiyun u32 timing_cfg_6; /* SDRAM Timing Configuration 6 */ 54*4882a593Smuzhiyun u32 timing_cfg_7; /* SDRAM Timing Configuration 7 */ 55*4882a593Smuzhiyun u32 ddr_zq_cntl; /* ZQ calibration control*/ 56*4882a593Smuzhiyun u32 ddr_wrlvl_cntl; /* write leveling control*/ 57*4882a593Smuzhiyun u8 reg_178[4]; 58*4882a593Smuzhiyun u32 ddr_sr_cntr; /* self refresh counter */ 59*4882a593Smuzhiyun u32 ddr_sdram_rcw_1; /* Control Words 1 */ 60*4882a593Smuzhiyun u32 ddr_sdram_rcw_2; /* Control Words 2 */ 61*4882a593Smuzhiyun u8 reg_188[8]; 62*4882a593Smuzhiyun u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */ 63*4882a593Smuzhiyun u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */ 64*4882a593Smuzhiyun u8 res_198[0x1a0-0x198]; 65*4882a593Smuzhiyun u32 ddr_sdram_rcw_3; 66*4882a593Smuzhiyun u32 ddr_sdram_rcw_4; 67*4882a593Smuzhiyun u32 ddr_sdram_rcw_5; 68*4882a593Smuzhiyun u32 ddr_sdram_rcw_6; 69*4882a593Smuzhiyun u8 res_1b0[0x200-0x1b0]; 70*4882a593Smuzhiyun u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */ 71*4882a593Smuzhiyun u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */ 72*4882a593Smuzhiyun u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */ 73*4882a593Smuzhiyun u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */ 74*4882a593Smuzhiyun u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */ 75*4882a593Smuzhiyun u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */ 76*4882a593Smuzhiyun u8 res_218[0x220-0x218]; 77*4882a593Smuzhiyun u32 sdram_mode_9; /* SDRAM Mode Configuration 9 */ 78*4882a593Smuzhiyun u32 sdram_mode_10; /* SDRAM Mode Configuration 10 */ 79*4882a593Smuzhiyun u32 sdram_mode_11; /* SDRAM Mode Configuration 11 */ 80*4882a593Smuzhiyun u32 sdram_mode_12; /* SDRAM Mode Configuration 12 */ 81*4882a593Smuzhiyun u32 sdram_mode_13; /* SDRAM Mode Configuration 13 */ 82*4882a593Smuzhiyun u32 sdram_mode_14; /* SDRAM Mode Configuration 14 */ 83*4882a593Smuzhiyun u32 sdram_mode_15; /* SDRAM Mode Configuration 15 */ 84*4882a593Smuzhiyun u32 sdram_mode_16; /* SDRAM Mode Configuration 16 */ 85*4882a593Smuzhiyun u8 res_240[0x250-0x240]; 86*4882a593Smuzhiyun u32 timing_cfg_8; /* SDRAM Timing Configuration 8 */ 87*4882a593Smuzhiyun u32 timing_cfg_9; /* SDRAM Timing Configuration 9 */ 88*4882a593Smuzhiyun u8 res_258[0x260-0x258]; 89*4882a593Smuzhiyun u32 sdram_cfg_3; 90*4882a593Smuzhiyun u8 res_264[0x400-0x264]; 91*4882a593Smuzhiyun u32 dq_map_0; 92*4882a593Smuzhiyun u32 dq_map_1; 93*4882a593Smuzhiyun u32 dq_map_2; 94*4882a593Smuzhiyun u32 dq_map_3; 95*4882a593Smuzhiyun u8 res_410[0xb20-0x410]; 96*4882a593Smuzhiyun u32 ddr_dsr1; /* Debug Status 1 */ 97*4882a593Smuzhiyun u32 ddr_dsr2; /* Debug Status 2 */ 98*4882a593Smuzhiyun u32 ddr_cdr1; /* Control Driver 1 */ 99*4882a593Smuzhiyun u32 ddr_cdr2; /* Control Driver 2 */ 100*4882a593Smuzhiyun u8 res_b30[200]; 101*4882a593Smuzhiyun u32 ip_rev1; /* IP Block Revision 1 */ 102*4882a593Smuzhiyun u32 ip_rev2; /* IP Block Revision 2 */ 103*4882a593Smuzhiyun u32 eor; /* Enhanced Optimization Register */ 104*4882a593Smuzhiyun u8 res_c04[252]; 105*4882a593Smuzhiyun u32 mtcr; /* Memory Test Control Register */ 106*4882a593Smuzhiyun u8 res_d04[28]; 107*4882a593Smuzhiyun u32 mtp1; /* Memory Test Pattern 1 */ 108*4882a593Smuzhiyun u32 mtp2; /* Memory Test Pattern 2 */ 109*4882a593Smuzhiyun u32 mtp3; /* Memory Test Pattern 3 */ 110*4882a593Smuzhiyun u32 mtp4; /* Memory Test Pattern 4 */ 111*4882a593Smuzhiyun u32 mtp5; /* Memory Test Pattern 5 */ 112*4882a593Smuzhiyun u32 mtp6; /* Memory Test Pattern 6 */ 113*4882a593Smuzhiyun u32 mtp7; /* Memory Test Pattern 7 */ 114*4882a593Smuzhiyun u32 mtp8; /* Memory Test Pattern 8 */ 115*4882a593Smuzhiyun u32 mtp9; /* Memory Test Pattern 9 */ 116*4882a593Smuzhiyun u32 mtp10; /* Memory Test Pattern 10 */ 117*4882a593Smuzhiyun u8 res_d48[184]; 118*4882a593Smuzhiyun u32 data_err_inject_hi; /* Data Path Err Injection Mask High */ 119*4882a593Smuzhiyun u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */ 120*4882a593Smuzhiyun u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */ 121*4882a593Smuzhiyun u8 res_e0c[20]; 122*4882a593Smuzhiyun u32 capture_data_hi; /* Data Path Read Capture High */ 123*4882a593Smuzhiyun u32 capture_data_lo; /* Data Path Read Capture Low */ 124*4882a593Smuzhiyun u32 capture_ecc; /* Data Path Read Capture ECC */ 125*4882a593Smuzhiyun u8 res_e2c[20]; 126*4882a593Smuzhiyun u32 err_detect; /* Error Detect */ 127*4882a593Smuzhiyun u32 err_disable; /* Error Disable */ 128*4882a593Smuzhiyun u32 err_int_en; 129*4882a593Smuzhiyun u32 capture_attributes; /* Error Attrs Capture */ 130*4882a593Smuzhiyun u32 capture_address; /* Error Addr Capture */ 131*4882a593Smuzhiyun u32 capture_ext_address; /* Error Extended Addr Capture */ 132*4882a593Smuzhiyun u32 err_sbe; /* Single-Bit ECC Error Management */ 133*4882a593Smuzhiyun u8 res_e5c[164]; 134*4882a593Smuzhiyun u32 debug[64]; /* debug_1 to debug_64 */ 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun #endif /* __FSL_IMMAP_H */ 137