1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2008-2014 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef DDR2_DIMM_PARAMS_H 8*4882a593Smuzhiyun #define DDR2_DIMM_PARAMS_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define EDC_DATA_PARITY 1 11*4882a593Smuzhiyun #define EDC_ECC 2 12*4882a593Smuzhiyun #define EDC_AC_PARITY 4 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Parameters for a DDR dimm computed from the SPD */ 15*4882a593Smuzhiyun typedef struct dimm_params_s { 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* DIMM organization parameters */ 18*4882a593Smuzhiyun char mpart[19]; /* guaranteed null terminated */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun unsigned int n_ranks; 21*4882a593Smuzhiyun unsigned long long rank_density; 22*4882a593Smuzhiyun unsigned long long capacity; 23*4882a593Smuzhiyun unsigned int data_width; 24*4882a593Smuzhiyun unsigned int primary_sdram_width; 25*4882a593Smuzhiyun unsigned int ec_sdram_width; 26*4882a593Smuzhiyun unsigned int registered_dimm; 27*4882a593Smuzhiyun unsigned int device_width; /* x4, x8, x16 components */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* SDRAM device parameters */ 30*4882a593Smuzhiyun unsigned int n_row_addr; 31*4882a593Smuzhiyun unsigned int n_col_addr; 32*4882a593Smuzhiyun unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */ 33*4882a593Smuzhiyun #ifdef CONFIG_SYS_FSL_DDR4 34*4882a593Smuzhiyun unsigned int bank_addr_bits; 35*4882a593Smuzhiyun unsigned int bank_group_bits; 36*4882a593Smuzhiyun #else 37*4882a593Smuzhiyun unsigned int n_banks_per_sdram_device; 38*4882a593Smuzhiyun #endif 39*4882a593Smuzhiyun unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */ 40*4882a593Smuzhiyun unsigned int row_density; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* used in computing base address of DIMMs */ 43*4882a593Smuzhiyun unsigned long long base_address; 44*4882a593Smuzhiyun /* mirrored DIMMs */ 45*4882a593Smuzhiyun unsigned int mirrored_dimm; /* only for ddr3 */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* DIMM timing parameters */ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun int mtb_ps; /* medium timebase ps */ 50*4882a593Smuzhiyun int ftb_10th_ps; /* fine timebase, in 1/10 ps */ 51*4882a593Smuzhiyun int taa_ps; /* minimum CAS latency time */ 52*4882a593Smuzhiyun int tfaw_ps; /* four active window delay */ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* 55*4882a593Smuzhiyun * SDRAM clock periods 56*4882a593Smuzhiyun * The range for these are 1000-10000 so a short should be sufficient 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun int tckmin_x_ps; 59*4882a593Smuzhiyun int tckmin_x_minus_1_ps; 60*4882a593Smuzhiyun int tckmin_x_minus_2_ps; 61*4882a593Smuzhiyun int tckmax_ps; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* SPD-defined CAS latencies */ 64*4882a593Smuzhiyun unsigned int caslat_x; 65*4882a593Smuzhiyun unsigned int caslat_x_minus_1; 66*4882a593Smuzhiyun unsigned int caslat_x_minus_2; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun unsigned int caslat_lowest_derated; /* Derated CAS latency */ 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* basic timing parameters */ 71*4882a593Smuzhiyun int trcd_ps; 72*4882a593Smuzhiyun int trp_ps; 73*4882a593Smuzhiyun int tras_ps; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #ifdef CONFIG_SYS_FSL_DDR4 76*4882a593Smuzhiyun int trfc1_ps; 77*4882a593Smuzhiyun int trfc2_ps; 78*4882a593Smuzhiyun int trfc4_ps; 79*4882a593Smuzhiyun int trrds_ps; 80*4882a593Smuzhiyun int trrdl_ps; 81*4882a593Smuzhiyun int tccdl_ps; 82*4882a593Smuzhiyun #else 83*4882a593Smuzhiyun int twr_ps; /* maximum = 63750 ps */ 84*4882a593Smuzhiyun int trfc_ps; /* max = 255 ns + 256 ns + .75 ns 85*4882a593Smuzhiyun = 511750 ps */ 86*4882a593Smuzhiyun int trrd_ps; /* maximum = 63750 ps */ 87*4882a593Smuzhiyun int twtr_ps; /* maximum = 63750 ps */ 88*4882a593Smuzhiyun int trtp_ps; /* byte 38, spd->trtp */ 89*4882a593Smuzhiyun #endif 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun int refresh_rate_ps; 94*4882a593Smuzhiyun int extended_op_srt; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) 97*4882a593Smuzhiyun int tis_ps; /* byte 32, spd->ca_setup */ 98*4882a593Smuzhiyun int tih_ps; /* byte 33, spd->ca_hold */ 99*4882a593Smuzhiyun int tds_ps; /* byte 34, spd->data_setup */ 100*4882a593Smuzhiyun int tdh_ps; /* byte 35, spd->data_hold */ 101*4882a593Smuzhiyun int tdqsq_max_ps; /* byte 44, spd->tdqsq */ 102*4882a593Smuzhiyun int tqhs_ps; /* byte 45, spd->tqhs */ 103*4882a593Smuzhiyun #endif 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* DDR3 RDIMM */ 106*4882a593Smuzhiyun unsigned char rcw[16]; /* Register Control Word 0-15 */ 107*4882a593Smuzhiyun #ifdef CONFIG_SYS_FSL_DDR4 108*4882a593Smuzhiyun unsigned int dq_mapping[18]; 109*4882a593Smuzhiyun unsigned int dq_mapping_ors; 110*4882a593Smuzhiyun #endif 111*4882a593Smuzhiyun } dimm_params_t; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, 114*4882a593Smuzhiyun const generic_spd_eeprom_t *spd, 115*4882a593Smuzhiyun dimm_params_t *pdimm, 116*4882a593Smuzhiyun unsigned int dimm_number); 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #endif 119