1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2015 Freescale Semiconductor 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __FSL_CSU_H__ 9*4882a593Smuzhiyun #define __FSL_CSU_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun enum csu_cslx_access { 12*4882a593Smuzhiyun CSU_NS_SUP_R = 0x08, 13*4882a593Smuzhiyun CSU_NS_SUP_W = 0x80, 14*4882a593Smuzhiyun CSU_NS_SUP_RW = 0x88, 15*4882a593Smuzhiyun CSU_NS_USER_R = 0x04, 16*4882a593Smuzhiyun CSU_NS_USER_W = 0x40, 17*4882a593Smuzhiyun CSU_NS_USER_RW = 0x44, 18*4882a593Smuzhiyun CSU_S_SUP_R = 0x02, 19*4882a593Smuzhiyun CSU_S_SUP_W = 0x20, 20*4882a593Smuzhiyun CSU_S_SUP_RW = 0x22, 21*4882a593Smuzhiyun CSU_S_USER_R = 0x01, 22*4882a593Smuzhiyun CSU_S_USER_W = 0x10, 23*4882a593Smuzhiyun CSU_S_USER_RW = 0x11, 24*4882a593Smuzhiyun CSU_ALL_RW = 0xff, 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun struct csu_ns_dev { 28*4882a593Smuzhiyun unsigned long ind; 29*4882a593Smuzhiyun uint32_t val; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun void enable_layerscape_ns_access(void); 33*4882a593Smuzhiyun void set_devices_ns_access(unsigned long, u16 val); 34*4882a593Smuzhiyun void set_pcie_ns_access(int pcie, u16 val); 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #endif 37