1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2015 Freescale Semiconductor 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __LDPAA_WRIOP_H 8*4882a593Smuzhiyun #define __LDPAA_WRIOP_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <phy.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun enum wriop_port { 13*4882a593Smuzhiyun WRIOP1_DPMAC1 = 1, 14*4882a593Smuzhiyun WRIOP1_DPMAC2, 15*4882a593Smuzhiyun WRIOP1_DPMAC3, 16*4882a593Smuzhiyun WRIOP1_DPMAC4, 17*4882a593Smuzhiyun WRIOP1_DPMAC5, 18*4882a593Smuzhiyun WRIOP1_DPMAC6, 19*4882a593Smuzhiyun WRIOP1_DPMAC7, 20*4882a593Smuzhiyun WRIOP1_DPMAC8, 21*4882a593Smuzhiyun WRIOP1_DPMAC9, 22*4882a593Smuzhiyun WRIOP1_DPMAC10, 23*4882a593Smuzhiyun WRIOP1_DPMAC11, 24*4882a593Smuzhiyun WRIOP1_DPMAC12, 25*4882a593Smuzhiyun WRIOP1_DPMAC13, 26*4882a593Smuzhiyun WRIOP1_DPMAC14, 27*4882a593Smuzhiyun WRIOP1_DPMAC15, 28*4882a593Smuzhiyun WRIOP1_DPMAC16, 29*4882a593Smuzhiyun WRIOP1_DPMAC17, 30*4882a593Smuzhiyun WRIOP1_DPMAC18, 31*4882a593Smuzhiyun WRIOP1_DPMAC19, 32*4882a593Smuzhiyun WRIOP1_DPMAC20, 33*4882a593Smuzhiyun WRIOP1_DPMAC21, 34*4882a593Smuzhiyun WRIOP1_DPMAC22, 35*4882a593Smuzhiyun WRIOP1_DPMAC23, 36*4882a593Smuzhiyun WRIOP1_DPMAC24, 37*4882a593Smuzhiyun NUM_WRIOP_PORTS, 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun struct wriop_dpmac_info { 41*4882a593Smuzhiyun u8 enabled; 42*4882a593Smuzhiyun u8 id; 43*4882a593Smuzhiyun u8 board_mux; 44*4882a593Smuzhiyun int phy_addr; 45*4882a593Smuzhiyun void *phy_regs; 46*4882a593Smuzhiyun phy_interface_t enet_if; 47*4882a593Smuzhiyun struct phy_device *phydev; 48*4882a593Smuzhiyun struct mii_dev *bus; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun extern struct wriop_dpmac_info dpmac_info[NUM_WRIOP_PORTS]; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define DEFAULT_WRIOP_MDIO1_NAME "FSL_MDIO0" 54*4882a593Smuzhiyun #define DEFAULT_WRIOP_MDIO2_NAME "FSL_MDIO1" 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun void wriop_init_dpmac(int, int, int); 57*4882a593Smuzhiyun void wriop_disable_dpmac(int); 58*4882a593Smuzhiyun void wriop_enable_dpmac(int); 59*4882a593Smuzhiyun u8 wriop_is_enabled_dpmac(int dpmac_id); 60*4882a593Smuzhiyun void wriop_set_mdio(int, struct mii_dev *); 61*4882a593Smuzhiyun struct mii_dev *wriop_get_mdio(int); 62*4882a593Smuzhiyun void wriop_set_phy_address(int, int); 63*4882a593Smuzhiyun int wriop_get_phy_address(int); 64*4882a593Smuzhiyun void wriop_set_phy_dev(int, struct phy_device *); 65*4882a593Smuzhiyun struct phy_device *wriop_get_phy_dev(int); 66*4882a593Smuzhiyun phy_interface_t wriop_get_enet_if(int); 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun void wriop_dpmac_disable(int); 69*4882a593Smuzhiyun void wriop_dpmac_enable(int); 70*4882a593Smuzhiyun phy_interface_t wriop_dpmac_enet_if(int, int); 71*4882a593Smuzhiyun void wriop_init_dpmac_qsgmii(int, int); 72*4882a593Smuzhiyun #endif /* __LDPAA_WRIOP_H */ 73