1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2014 Freescale Semiconductor 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __FSL_MC_H__ 8*4882a593Smuzhiyun #define __FSL_MC_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define MC_CCSR_BASE_ADDR \ 13*4882a593Smuzhiyun ((struct mc_ccsr_registers __iomem *)0x8340000) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define GCR1_P1_STOP BIT(31) 16*4882a593Smuzhiyun #define GCR1_P2_STOP BIT(30) 17*4882a593Smuzhiyun #define GCR1_P1_DE_RST BIT(23) 18*4882a593Smuzhiyun #define GCR1_P2_DE_RST BIT(22) 19*4882a593Smuzhiyun #define GCR1_M1_DE_RST BIT(15) 20*4882a593Smuzhiyun #define GCR1_M2_DE_RST BIT(14) 21*4882a593Smuzhiyun #define GCR1_M_ALL_DE_RST (GCR1_M1_DE_RST | GCR1_M2_DE_RST) 22*4882a593Smuzhiyun #define GSR_FS_MASK 0x3fffffff 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define SOC_MC_PORTALS_BASE_ADDR ((void __iomem *)0x00080C000000) 25*4882a593Smuzhiyun #define SOC_QBMAN_PORTALS_BASE_ADDR ((void __iomem *)0x000818000000) 26*4882a593Smuzhiyun #define SOC_MC_PORTAL_STRIDE 0x10000 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define SOC_MC_PORTAL_ADDR(_portal_id) \ 29*4882a593Smuzhiyun ((void __iomem *)((uintptr_t)SOC_MC_PORTALS_BASE_ADDR + \ 30*4882a593Smuzhiyun (_portal_id) * SOC_MC_PORTAL_STRIDE)) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define MC_PORTAL_OFFSET_TO_PORTAL_ID(_portal_offset) \ 33*4882a593Smuzhiyun ((_portal_offset) / SOC_MC_PORTAL_STRIDE) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun struct mc_ccsr_registers { 36*4882a593Smuzhiyun u32 reg_gcr1; 37*4882a593Smuzhiyun u32 reserved1; 38*4882a593Smuzhiyun u32 reg_gsr; 39*4882a593Smuzhiyun u32 reserved2; 40*4882a593Smuzhiyun u32 reg_sicbalr; 41*4882a593Smuzhiyun u32 reg_sicbahr; 42*4882a593Smuzhiyun u32 reg_sicapr; 43*4882a593Smuzhiyun u32 reserved3; 44*4882a593Smuzhiyun u32 reg_mcfbalr; 45*4882a593Smuzhiyun u32 reg_mcfbahr; 46*4882a593Smuzhiyun u32 reg_mcfapr; 47*4882a593Smuzhiyun u32 reserved4[0x2f1]; 48*4882a593Smuzhiyun u32 reg_psr; 49*4882a593Smuzhiyun u32 reserved5; 50*4882a593Smuzhiyun u32 reg_brr[2]; 51*4882a593Smuzhiyun u32 reserved6[0x80]; 52*4882a593Smuzhiyun u32 reg_error[]; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun int get_mc_boot_status(void); 56*4882a593Smuzhiyun int get_dpl_apply_status(void); 57*4882a593Smuzhiyun #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 58*4882a593Smuzhiyun int get_aiop_apply_status(void); 59*4882a593Smuzhiyun #endif 60*4882a593Smuzhiyun u64 mc_get_dram_addr(void); 61*4882a593Smuzhiyun unsigned long mc_get_dram_block_size(void); 62*4882a593Smuzhiyun int fsl_mc_ldpaa_init(bd_t *bis); 63*4882a593Smuzhiyun int fsl_mc_ldpaa_exit(bd_t *bd); 64*4882a593Smuzhiyun void mc_env_boot(void); 65*4882a593Smuzhiyun #endif 66