1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2002 3*4882a593Smuzhiyun * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <linux/types.h> /* for ulong typedef */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _FPGA_H_ 11*4882a593Smuzhiyun #define _FPGA_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef CONFIG_MAX_FPGA_DEVICES 14*4882a593Smuzhiyun #define CONFIG_MAX_FPGA_DEVICES 5 15*4882a593Smuzhiyun #endif 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* fpga_xxxx function return value definitions */ 18*4882a593Smuzhiyun #define FPGA_SUCCESS 0 19*4882a593Smuzhiyun #define FPGA_FAIL -1 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* device numbers must be non-negative */ 22*4882a593Smuzhiyun #define FPGA_INVALID_DEVICE -1 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* root data type defintions */ 25*4882a593Smuzhiyun typedef enum { /* typedef fpga_type */ 26*4882a593Smuzhiyun fpga_min_type, /* range check value */ 27*4882a593Smuzhiyun fpga_xilinx, /* Xilinx Family) */ 28*4882a593Smuzhiyun fpga_altera, /* unimplemented */ 29*4882a593Smuzhiyun fpga_lattice, /* Lattice family */ 30*4882a593Smuzhiyun fpga_undefined /* invalid range check value */ 31*4882a593Smuzhiyun } fpga_type; /* end, typedef fpga_type */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun typedef struct { /* typedef fpga_desc */ 34*4882a593Smuzhiyun fpga_type devtype; /* switch value to select sub-functions */ 35*4882a593Smuzhiyun void *devdesc; /* real device descriptor */ 36*4882a593Smuzhiyun } fpga_desc; /* end, typedef fpga_desc */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun typedef struct { /* typedef fpga_desc */ 39*4882a593Smuzhiyun unsigned int blocksize; 40*4882a593Smuzhiyun char *interface; 41*4882a593Smuzhiyun char *dev_part; 42*4882a593Smuzhiyun char *filename; 43*4882a593Smuzhiyun int fstype; 44*4882a593Smuzhiyun } fpga_fs_info; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun typedef enum { 47*4882a593Smuzhiyun BIT_FULL = 0, 48*4882a593Smuzhiyun BIT_PARTIAL, 49*4882a593Smuzhiyun BIT_NONE = 0xFF, 50*4882a593Smuzhiyun } bitstream_type; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* root function definitions */ 53*4882a593Smuzhiyun void fpga_init(void); 54*4882a593Smuzhiyun int fpga_add(fpga_type devtype, void *desc); 55*4882a593Smuzhiyun int fpga_count(void); 56*4882a593Smuzhiyun const fpga_desc *const fpga_get_desc(int devnum); 57*4882a593Smuzhiyun int fpga_load(int devnum, const void *buf, size_t bsize, 58*4882a593Smuzhiyun bitstream_type bstype); 59*4882a593Smuzhiyun int fpga_fsload(int devnum, const void *buf, size_t size, 60*4882a593Smuzhiyun fpga_fs_info *fpga_fsinfo); 61*4882a593Smuzhiyun int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, 62*4882a593Smuzhiyun bitstream_type bstype); 63*4882a593Smuzhiyun int fpga_dump(int devnum, const void *buf, size_t bsize); 64*4882a593Smuzhiyun int fpga_info(int devnum); 65*4882a593Smuzhiyun const fpga_desc *const fpga_validate(int devnum, const void *buf, 66*4882a593Smuzhiyun size_t bsize, char *fn); 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #endif /* _FPGA_H_ */ 69