1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Watchdog driver for the FTWDT010 Watch Dog Driver 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (c) Copyright 2004 Faraday Technology Corp. (www.faraday-tech.com) 5*4882a593Smuzhiyun * Based on sa1100_wdt.c by Oleg Drokin <green@crimea.edu> 6*4882a593Smuzhiyun * Based on SoftDog driver by Alan Cox <alan@redhat.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 2011 Andes Technology Corporation 9*4882a593Smuzhiyun * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * 27/11/2004 Initial release, Faraday. 14*4882a593Smuzhiyun * 12/01/2011 Port to u-boot, Macpaul Lin. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef __FTWDT010_H 18*4882a593Smuzhiyun #define __FTWDT010_H 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun struct ftwdt010_wdt { 21*4882a593Smuzhiyun unsigned int wdcounter; /* Counter Reg - 0x00 */ 22*4882a593Smuzhiyun unsigned int wdload; /* Counter Auto Reload Reg - 0x04 */ 23*4882a593Smuzhiyun unsigned int wdrestart; /* Counter Restart Reg - 0x08 */ 24*4882a593Smuzhiyun unsigned int wdcr; /* Control Reg - 0x0c */ 25*4882a593Smuzhiyun unsigned int wdstatus; /* Status Reg - 0x10 */ 26*4882a593Smuzhiyun unsigned int wdclear; /* Timer Clear - 0x14 */ 27*4882a593Smuzhiyun unsigned int wdintrlen; /* Interrupt Length - 0x18 */ 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* 31*4882a593Smuzhiyun * WDLOAD - Counter Auto Reload Register 32*4882a593Smuzhiyun * The Auto Reload Register is set to 0x03EF1480 (66Mhz) by default. 33*4882a593Smuzhiyun * Which means in a 66MHz system, the period of Watch Dog timer reset is 34*4882a593Smuzhiyun * one second. 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun #define FTWDT010_WDLOAD(x) ((x) & 0xffffffff) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* 39*4882a593Smuzhiyun * WDRESTART - Watch Dog Timer Counter Restart Register 40*4882a593Smuzhiyun * If writing 0x5AB9 to WDRESTART register, Watch Dog timer will 41*4882a593Smuzhiyun * automatically reload WDLOAD to WDCOUNTER and restart counting. 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun #define FTWDT010_WDRESTART_MAGIC 0x5AB9 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* WDCR - Watch Dog Timer Control Register */ 46*4882a593Smuzhiyun #define FTWDT010_WDCR_ENABLE (1 << 0) 47*4882a593Smuzhiyun #define FTWDT010_WDCR_RST (1 << 1) 48*4882a593Smuzhiyun #define FTWDT010_WDCR_INTR (1 << 2) 49*4882a593Smuzhiyun /* FTWDT010_WDCR_EXT bit: Watch Dog Timer External Signal Enable */ 50*4882a593Smuzhiyun #define FTWDT010_WDCR_EXT (1 << 3) 51*4882a593Smuzhiyun /* FTWDT010_WDCR_CLOCK bit: Clock Source: 0: PCLK, 1: EXTCLK. 52*4882a593Smuzhiyun * The clock source PCLK cannot be gated when system sleeps, even if 53*4882a593Smuzhiyun * WDCLOCK bit is turned on. 54*4882a593Smuzhiyun * 55*4882a593Smuzhiyun * Faraday's Watch Dog timer can be driven by an external clock. The 56*4882a593Smuzhiyun * programmer just needs to write one to WdCR[WdClock] bit. 57*4882a593Smuzhiyun * 58*4882a593Smuzhiyun * Note: There is a limitation between EXTCLK and PCLK: 59*4882a593Smuzhiyun * EXTCLK cycle time / PCLK cycle time > 2. 60*4882a593Smuzhiyun * If the system does not need an external clock, 61*4882a593Smuzhiyun * just keep WdCR[WdClock] bit in its default value. 62*4882a593Smuzhiyun */ 63*4882a593Smuzhiyun #define FTWDT010_WDCR_CLOCK (1 << 4) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* 66*4882a593Smuzhiyun * WDSTATUS - Watch Dog Timer Status Register 67*4882a593Smuzhiyun * This bit is set when the counter reaches Zero 68*4882a593Smuzhiyun */ 69*4882a593Smuzhiyun #define FTWDT010_WDSTATUS(x) ((x) & 0x1) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* 72*4882a593Smuzhiyun * WDCLEAR - Watch Dog Timer Clear Register 73*4882a593Smuzhiyun * Writing one to this register will clear WDSTATUS. 74*4882a593Smuzhiyun */ 75*4882a593Smuzhiyun #define FTWDT010_WDCLEAR (1 << 0) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* 78*4882a593Smuzhiyun * WDINTRLEN - Watch Dog Timer Interrupt Length 79*4882a593Smuzhiyun * This register controls the duration length of wd_rst, wd_intr and wd_ext. 80*4882a593Smuzhiyun * The default value is 0xFF. 81*4882a593Smuzhiyun */ 82*4882a593Smuzhiyun #define FTWDT010_WDINTRLEN(x) ((x) & 0xff) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* 85*4882a593Smuzhiyun * Variable timeout should be set in ms. 86*4882a593Smuzhiyun * (CONFIG_SYS_CLK_FREQ/1000) equals 1 ms. 87*4882a593Smuzhiyun * WDLOAD = timeout * TIMEOUT_FACTOR. 88*4882a593Smuzhiyun */ 89*4882a593Smuzhiyun #define FTWDT010_TIMEOUT_FACTOR (CONFIG_SYS_CLK_FREQ / 1000) /* 1 ms */ 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun void ftwdt010_wdt_reset(void); 92*4882a593Smuzhiyun void ftwdt010_wdt_disable(void); 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #endif /* __FTWDT010_H */ 95