1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2009 Faraday Technology 3*4882a593Smuzhiyun * Po-Yu Chuang <ratbert@faraday-tech.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* 9*4882a593Smuzhiyun * Timer 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun #ifndef __FTTMR010_H 12*4882a593Smuzhiyun #define __FTTMR010_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct fttmr010 { 15*4882a593Smuzhiyun unsigned int timer1_counter; /* 0x00 */ 16*4882a593Smuzhiyun unsigned int timer1_load; /* 0x04 */ 17*4882a593Smuzhiyun unsigned int timer1_match1; /* 0x08 */ 18*4882a593Smuzhiyun unsigned int timer1_match2; /* 0x0c */ 19*4882a593Smuzhiyun unsigned int timer2_counter; /* 0x10 */ 20*4882a593Smuzhiyun unsigned int timer2_load; /* 0x14 */ 21*4882a593Smuzhiyun unsigned int timer2_match1; /* 0x18 */ 22*4882a593Smuzhiyun unsigned int timer2_match2; /* 0x1c */ 23*4882a593Smuzhiyun unsigned int timer3_counter; /* 0x20 */ 24*4882a593Smuzhiyun unsigned int timer3_load; /* 0x24 */ 25*4882a593Smuzhiyun unsigned int timer3_match1; /* 0x28 */ 26*4882a593Smuzhiyun unsigned int timer3_match2; /* 0x2c */ 27*4882a593Smuzhiyun unsigned int cr; /* 0x30 */ 28*4882a593Smuzhiyun unsigned int interrupt_state; /* 0x34 */ 29*4882a593Smuzhiyun unsigned int interrupt_mask; /* 0x38 */ 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* 33*4882a593Smuzhiyun * Timer Control Register 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun #define FTTMR010_TM3_UPDOWN (1 << 11) 36*4882a593Smuzhiyun #define FTTMR010_TM2_UPDOWN (1 << 10) 37*4882a593Smuzhiyun #define FTTMR010_TM1_UPDOWN (1 << 9) 38*4882a593Smuzhiyun #define FTTMR010_TM3_OFENABLE (1 << 8) 39*4882a593Smuzhiyun #define FTTMR010_TM3_CLOCK (1 << 7) 40*4882a593Smuzhiyun #define FTTMR010_TM3_ENABLE (1 << 6) 41*4882a593Smuzhiyun #define FTTMR010_TM2_OFENABLE (1 << 5) 42*4882a593Smuzhiyun #define FTTMR010_TM2_CLOCK (1 << 4) 43*4882a593Smuzhiyun #define FTTMR010_TM2_ENABLE (1 << 3) 44*4882a593Smuzhiyun #define FTTMR010_TM1_OFENABLE (1 << 2) 45*4882a593Smuzhiyun #define FTTMR010_TM1_CLOCK (1 << 1) 46*4882a593Smuzhiyun #define FTTMR010_TM1_ENABLE (1 << 0) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* 49*4882a593Smuzhiyun * Timer Interrupt State & Mask Registers 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun #define FTTMR010_TM3_OVERFLOW (1 << 8) 52*4882a593Smuzhiyun #define FTTMR010_TM3_MATCH2 (1 << 7) 53*4882a593Smuzhiyun #define FTTMR010_TM3_MATCH1 (1 << 6) 54*4882a593Smuzhiyun #define FTTMR010_TM2_OVERFLOW (1 << 5) 55*4882a593Smuzhiyun #define FTTMR010_TM2_MATCH2 (1 << 4) 56*4882a593Smuzhiyun #define FTTMR010_TM2_MATCH1 (1 << 3) 57*4882a593Smuzhiyun #define FTTMR010_TM1_OVERFLOW (1 << 2) 58*4882a593Smuzhiyun #define FTTMR010_TM1_MATCH2 (1 << 1) 59*4882a593Smuzhiyun #define FTTMR010_TM1_MATCH1 (1 << 0) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #endif /* __FTTMR010_H */ 62