1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2009 Faraday Technology 3*4882a593Smuzhiyun * Po-Yu Chuang <ratbert@faraday-tech.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* 9*4882a593Smuzhiyun * Static Memory Controller 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun #ifndef __FTSMC020_H 12*4882a593Smuzhiyun #define __FTSMC020_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun struct ftsmc020_bank { 17*4882a593Smuzhiyun unsigned int cr; 18*4882a593Smuzhiyun unsigned int tpr; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun struct ftsmc020 { 22*4882a593Smuzhiyun struct ftsmc020_bank bank[4]; /* 0x00 - 0x1c */ 23*4882a593Smuzhiyun unsigned int pad[8]; /* 0x20 - 0x3c */ 24*4882a593Smuzhiyun unsigned int ssr; /* 0x40 */ 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun void ftsmc020_init(void); 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * Memory Bank Configuration Register 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun #define FTSMC020_BANK_ENABLE (1 << 28) 35*4882a593Smuzhiyun #define FTSMC020_BANK_BASE(x) ((x) & 0x0fff1000) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define FTSMC020_BANK_WPROT (1 << 11) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define FTSMC020_BANK_TYPE1 (1 << 10) 40*4882a593Smuzhiyun #define FTSMC020_BANK_TYPE2 (1 << 9) 41*4882a593Smuzhiyun #define FTSMC020_BANK_TYPE3 (1 << 8) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define FTSMC020_BANK_SIZE_32K (0xb << 4) 44*4882a593Smuzhiyun #define FTSMC020_BANK_SIZE_64K (0xc << 4) 45*4882a593Smuzhiyun #define FTSMC020_BANK_SIZE_128K (0xd << 4) 46*4882a593Smuzhiyun #define FTSMC020_BANK_SIZE_256K (0xe << 4) 47*4882a593Smuzhiyun #define FTSMC020_BANK_SIZE_512K (0xf << 4) 48*4882a593Smuzhiyun #define FTSMC020_BANK_SIZE_1M (0x0 << 4) 49*4882a593Smuzhiyun #define FTSMC020_BANK_SIZE_2M (0x1 << 4) 50*4882a593Smuzhiyun #define FTSMC020_BANK_SIZE_4M (0x2 << 4) 51*4882a593Smuzhiyun #define FTSMC020_BANK_SIZE_8M (0x3 << 4) 52*4882a593Smuzhiyun #define FTSMC020_BANK_SIZE_16M (0x4 << 4) 53*4882a593Smuzhiyun #define FTSMC020_BANK_SIZE_32M (0x5 << 4) 54*4882a593Smuzhiyun #define FTSMC020_BANK_SIZE_64M (0x6 << 4) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define FTSMC020_BANK_MBW_8 (0x0 << 0) 57*4882a593Smuzhiyun #define FTSMC020_BANK_MBW_16 (0x1 << 0) 58*4882a593Smuzhiyun #define FTSMC020_BANK_MBW_32 (0x2 << 0) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* 61*4882a593Smuzhiyun * Memory Bank Timing Parameter Register 62*4882a593Smuzhiyun */ 63*4882a593Smuzhiyun #define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28) 64*4882a593Smuzhiyun #define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24) 65*4882a593Smuzhiyun #define FTSMC020_TPR_RBE (1 << 20) 66*4882a593Smuzhiyun #define FTSMC020_TPR_AST(x) (((x) & 0x3) << 18) 67*4882a593Smuzhiyun #define FTSMC020_TPR_CTW(x) (((x) & 0x3) << 16) 68*4882a593Smuzhiyun #define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12) 69*4882a593Smuzhiyun #define FTSMC020_TPR_AT2(x) (((x) & 0x3) << 8) 70*4882a593Smuzhiyun #define FTSMC020_TPR_WTC(x) (((x) & 0x3) << 6) 71*4882a593Smuzhiyun #define FTSMC020_TPR_AHT(x) (((x) & 0x3) << 4) 72*4882a593Smuzhiyun #define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #endif /* __FTSMC020_H */ 75