1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2009 Faraday Technology 3*4882a593Smuzhiyun * Po-Yu Chuang <ratbert@faraday-tech.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * (C) Copyright 2011 Andes Technology Corp 6*4882a593Smuzhiyun * Macpaul Lin <macpaul@andestech.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * FTSDMC021 - SDRAM Controller 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun #ifndef __FTSDMC021_H 15*4882a593Smuzhiyun #define __FTSDMC021_H 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 18*4882a593Smuzhiyun struct ftsdmc021 { 19*4882a593Smuzhiyun unsigned int tp1; /* 0x00 - SDRAM Timing Parameter 1 */ 20*4882a593Smuzhiyun unsigned int tp2; /* 0x04 - SDRAM Timing Parameter 2 */ 21*4882a593Smuzhiyun unsigned int cr1; /* 0x08 - SDRAM Configuration Reg 1 */ 22*4882a593Smuzhiyun unsigned int cr2; /* 0x0c - SDRAM Configuration Reg 2 */ 23*4882a593Smuzhiyun unsigned int bank0_bsr; /* 0x10 - Ext. Bank Base/Size Reg 0 */ 24*4882a593Smuzhiyun unsigned int bank1_bsr; /* 0x14 - Ext. Bank Base/Size Reg 1 */ 25*4882a593Smuzhiyun unsigned int bank2_bsr; /* 0x18 - Ext. Bank Base/Size Reg 2 */ 26*4882a593Smuzhiyun unsigned int bank3_bsr; /* 0x1c - Ext. Bank Base/Size Reg 3 */ 27*4882a593Smuzhiyun unsigned int bank4_bsr; /* 0x20 - Ext. Bank Base/Size Reg 4 */ 28*4882a593Smuzhiyun unsigned int bank5_bsr; /* 0x24 - Ext. Bank Base/Size Reg 5 */ 29*4882a593Smuzhiyun unsigned int bank6_bsr; /* 0x28 - Ext. Bank Base/Size Reg 6 */ 30*4882a593Smuzhiyun unsigned int bank7_bsr; /* 0x2c - Ext. Bank Base/Size Reg 7 */ 31*4882a593Smuzhiyun unsigned int ragr; /* 0x30 - Read Arbitration Group Reg */ 32*4882a593Smuzhiyun unsigned int frr; /* 0x34 - Flush Request Register */ 33*4882a593Smuzhiyun unsigned int ebisr; /* 0x38 - EBI Support Register */ 34*4882a593Smuzhiyun unsigned int rsved[25]; /* 0x3c-0x9c - Reserved */ 35*4882a593Smuzhiyun unsigned int crr; /* 0x100 - Controller Revision Reg */ 36*4882a593Smuzhiyun unsigned int cfr; /* 0x104 - Controller Feature Reg */ 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* 41*4882a593Smuzhiyun * Timing Parameter 1 Register 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun #define FTSDMC021_TP1_TCL(x) ((x) & 0x3) /* CAS Latency */ 44*4882a593Smuzhiyun #define FTSDMC021_TP1_TWR(x) (((x) & 0x3) << 4) /* W-Recovery Time */ 45*4882a593Smuzhiyun #define FTSDMC021_TP1_TRF(x) (((x) & 0xf) << 8) /* Auto-Refresh Cycle */ 46*4882a593Smuzhiyun #define FTSDMC021_TP1_TRCD(x) (((x) & 0x7) << 12) /* RAS-to-CAS Delay */ 47*4882a593Smuzhiyun #define FTSDMC021_TP1_TRP(x) (((x) & 0xf) << 16) /* Precharge Cycle */ 48*4882a593Smuzhiyun #define FTSDMC021_TP1_TRAS(x) (((x) & 0xf) << 20) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* 51*4882a593Smuzhiyun * Timing Parameter 2 Register 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun #define FTSDMC021_TP2_REF_INTV(x) ((x) & 0xffff) /* Refresh interval */ 54*4882a593Smuzhiyun /* b(16:19) - Initial Refresh Times */ 55*4882a593Smuzhiyun #define FTSDMC021_TP2_INI_REFT(x) (((x) & 0xf) << 16) 56*4882a593Smuzhiyun /* b(20:23) - Initial Pre-Charge Times */ 57*4882a593Smuzhiyun #define FTSDMC021_TP2_INI_PREC(x) (((x) & 0xf) << 20) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* 60*4882a593Smuzhiyun * SDRAM Configuration Register 1 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun #define FTSDMC021_CR1_BNKSIZE(x) ((x) & 0xf) /* Bank Size */ 63*4882a593Smuzhiyun #define FTSDMC021_CR1_MBW(x) (((x) & 0x3) << 4) /* Bus Width */ 64*4882a593Smuzhiyun #define FTSDMC021_CR1_DSZ(x) (((x) & 0x7) << 8) /* SDRAM Size */ 65*4882a593Smuzhiyun #define FTSDMC021_CR1_DDW(x) (((x) & 0x3) << 12) /* Data Width */ 66*4882a593Smuzhiyun /* b(16) MA2T: Double Memory Address Cycle Enable */ 67*4882a593Smuzhiyun #define FTSDMC021_CR1_MA2T(x) (1 << 16) 68*4882a593Smuzhiyun /* The value of b(0:3)CR1: 1M-512M, must be power of 2 */ 69*4882a593Smuzhiyun #define FTSDMC021_BANK_SIZE(x) (ffs(x) - 1) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* 72*4882a593Smuzhiyun * Configuration Register 2 73*4882a593Smuzhiyun */ 74*4882a593Smuzhiyun #define FTSDMC021_CR2_SREF (1 << 0) /* Self-Refresh Mode */ 75*4882a593Smuzhiyun #define FTSDMC021_CR2_PWDN (1 << 1) /* Power Down Operation Mode */ 76*4882a593Smuzhiyun #define FTSDMC021_CR2_ISMR (1 << 2) /* Start Set-Mode-Register */ 77*4882a593Smuzhiyun #define FTSDMC021_CR2_IREF (1 << 3) /* Init Refresh Start Flag */ 78*4882a593Smuzhiyun #define FTSDMC021_CR2_IPREC (1 << 4) /* Init Pre-Charge Start Flag */ 79*4882a593Smuzhiyun #define FTSDMC021_CR2_REFTYPE (1 << 5) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* 82*4882a593Smuzhiyun * SDRAM External Bank Base/Size Register 83*4882a593Smuzhiyun */ 84*4882a593Smuzhiyun #define FTSDMC021_BANK_ENABLE (1 << 12) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* 12-bit base address of external bank. 87*4882a593Smuzhiyun * Default value is 0x800. 88*4882a593Smuzhiyun * The 12-bit equals to the haddr[31:20] of AHB address bus. */ 89*4882a593Smuzhiyun #define FTSDMC021_BANK_BASE(x) ((x) & 0xfff) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* 92*4882a593Smuzhiyun * Read Arbitration Grant Window Register 93*4882a593Smuzhiyun */ 94*4882a593Smuzhiyun #define FTSDMC021_RAGR_CH1GW(x) (((x) & 0xff) << 0) 95*4882a593Smuzhiyun #define FTSDMC021_RAGR_CH2GW(x) (((x) & 0xff) << 4) 96*4882a593Smuzhiyun #define FTSDMC021_RAGR_CH3GW(x) (((x) & 0xff) << 8) 97*4882a593Smuzhiyun #define FTSDMC021_RAGR_CH4GW(x) (((x) & 0xff) << 12) 98*4882a593Smuzhiyun #define FTSDMC021_RAGR_CH5GW(x) (((x) & 0xff) << 16) 99*4882a593Smuzhiyun #define FTSDMC021_RAGR_CH6GW(x) (((x) & 0xff) << 20) 100*4882a593Smuzhiyun #define FTSDMC021_RAGR_CH7GW(x) (((x) & 0xff) << 24) 101*4882a593Smuzhiyun #define FTSDMC021_RAGR_CH8GW(x) (((x) & 0xff) << 28) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* 104*4882a593Smuzhiyun * Flush Request Register 105*4882a593Smuzhiyun */ 106*4882a593Smuzhiyun #define FTSDMC021_FRR_FLUSHCHN(x) (((x) & 0x7) << 0) 107*4882a593Smuzhiyun #define FTSDMC021_FRR_FLUSHCMPLT (1 << 3) /* Flush Req Flag */ 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* 110*4882a593Smuzhiyun * External Bus Interface Support Register (EBISR) 111*4882a593Smuzhiyun */ 112*4882a593Smuzhiyun #define FTSDMC021_EBISR_MR(x) ((x) & 0xfff) /* Far-end mode */ 113*4882a593Smuzhiyun #define FTSDMC021_EBISR_PRSMR (1 << 12) /* Pre-SMR */ 114*4882a593Smuzhiyun #define FTSDMC021_EBISR_POPREC (1 << 13) 115*4882a593Smuzhiyun #define FTSDMC021_EBISR_POSMR (1 << 14) /* Post-SMR */ 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* 118*4882a593Smuzhiyun * Controller Revision Register (CRR, Read Only) 119*4882a593Smuzhiyun */ 120*4882a593Smuzhiyun #define FTSDMC021_CRR_REV_VER (((x) >> 0) & 0xff) 121*4882a593Smuzhiyun #define FTSDMC021_CRR_MINOR_VER (((x) >> 8) & 0xff) 122*4882a593Smuzhiyun #define FTSDMC021_CRR_MAJOR_VER (((x) >> 16) & 0xff) 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* 125*4882a593Smuzhiyun * Controller Feature Register (CFR, Read Only) 126*4882a593Smuzhiyun */ 127*4882a593Smuzhiyun #define FTSDMC021_CFR_EBNK (((x) >> 0) & 0xf) 128*4882a593Smuzhiyun #define FTSDMC021_CFR_CHN (((x) >> 8) & 0xf) 129*4882a593Smuzhiyun #define FTSDMC021_CFR_EBI (((x) >> 16) & 0x1) 130*4882a593Smuzhiyun #define FTSDMC021_CFR_CH1_FDEPTH (((x) >> 24) & 0x1) 131*4882a593Smuzhiyun #define FTSDMC021_CFR_CH2_FDEPTH (((x) >> 25) & 0x1) 132*4882a593Smuzhiyun #define FTSDMC021_CFR_CH3_FDEPTH (((x) >> 26) & 0x1) 133*4882a593Smuzhiyun #define FTSDMC021_CFR_CH4_FDEPTH (((x) >> 27) & 0x1) 134*4882a593Smuzhiyun #define FTSDMC021_CFR_CH5_FDEPTH (((x) >> 28) & 0x1) 135*4882a593Smuzhiyun #define FTSDMC021_CFR_CH6_FDEPTH (((x) >> 29) & 0x1) 136*4882a593Smuzhiyun #define FTSDMC021_CFR_CH7_FDEPTH (((x) >> 30) & 0x1) 137*4882a593Smuzhiyun #define FTSDMC021_CFR_CH8_FDEPTH (((x) >> 31) & 0x1) 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun #endif /* __FTSDMC021_H */ 140