1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2009 Faraday Technology 3*4882a593Smuzhiyun * Po-Yu Chuang <ratbert@faraday-tech.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* 9*4882a593Smuzhiyun * SDRAM Controller 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun #ifndef __FTSDMC020_H 12*4882a593Smuzhiyun #define __FTSDMC020_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define FTSDMC020_OFFSET_TP0 0x00 15*4882a593Smuzhiyun #define FTSDMC020_OFFSET_TP1 0x04 16*4882a593Smuzhiyun #define FTSDMC020_OFFSET_CR 0x08 17*4882a593Smuzhiyun #define FTSDMC020_OFFSET_BANK0_BSR 0x0C 18*4882a593Smuzhiyun #define FTSDMC020_OFFSET_BANK1_BSR 0x10 19*4882a593Smuzhiyun #define FTSDMC020_OFFSET_BANK2_BSR 0x14 20*4882a593Smuzhiyun #define FTSDMC020_OFFSET_BANK3_BSR 0x18 21*4882a593Smuzhiyun #define FTSDMC020_OFFSET_BANK4_BSR 0x1C 22*4882a593Smuzhiyun #define FTSDMC020_OFFSET_BANK5_BSR 0x20 23*4882a593Smuzhiyun #define FTSDMC020_OFFSET_BANK6_BSR 0x24 24*4882a593Smuzhiyun #define FTSDMC020_OFFSET_BANK7_BSR 0x28 25*4882a593Smuzhiyun #define FTSDMC020_OFFSET_ACR 0x34 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* 28*4882a593Smuzhiyun * Timing Parametet 0 Register 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun #define FTSDMC020_TP0_TCL(x) ((x) & 0x3) 31*4882a593Smuzhiyun #define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4) 32*4882a593Smuzhiyun #define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8) 33*4882a593Smuzhiyun #define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12) 34*4882a593Smuzhiyun #define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16) 35*4882a593Smuzhiyun #define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* 38*4882a593Smuzhiyun * Timing Parametet 1 Register 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun #define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff) 41*4882a593Smuzhiyun #define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16) 42*4882a593Smuzhiyun #define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* 45*4882a593Smuzhiyun * Configuration Register 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun #define FTSDMC020_CR_SREF (1 << 0) 48*4882a593Smuzhiyun #define FTSDMC020_CR_PWDN (1 << 1) 49*4882a593Smuzhiyun #define FTSDMC020_CR_ISMR (1 << 2) 50*4882a593Smuzhiyun #define FTSDMC020_CR_IREF (1 << 3) 51*4882a593Smuzhiyun #define FTSDMC020_CR_IPREC (1 << 4) 52*4882a593Smuzhiyun #define FTSDMC020_CR_REFTYPE (1 << 5) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* 55*4882a593Smuzhiyun * SDRAM External Bank Base/Size Register 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun #define FTSDMC020_BANK_ENABLE (1 << 28) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define FTSDMC020_BANK_DDW_X4 (0 << 12) 62*4882a593Smuzhiyun #define FTSDMC020_BANK_DDW_X8 (1 << 12) 63*4882a593Smuzhiyun #define FTSDMC020_BANK_DDW_X16 (2 << 12) 64*4882a593Smuzhiyun #define FTSDMC020_BANK_DDW_X32 (3 << 12) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define FTSDMC020_BANK_DSZ_16M (0 << 8) 67*4882a593Smuzhiyun #define FTSDMC020_BANK_DSZ_64M (1 << 8) 68*4882a593Smuzhiyun #define FTSDMC020_BANK_DSZ_128M (2 << 8) 69*4882a593Smuzhiyun #define FTSDMC020_BANK_DSZ_256M (3 << 8) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define FTSDMC020_BANK_MBW_8 (0 << 4) 72*4882a593Smuzhiyun #define FTSDMC020_BANK_MBW_16 (1 << 4) 73*4882a593Smuzhiyun #define FTSDMC020_BANK_MBW_32 (2 << 4) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define FTSDMC020_BANK_SIZE_1M 0x0 76*4882a593Smuzhiyun #define FTSDMC020_BANK_SIZE_2M 0x1 77*4882a593Smuzhiyun #define FTSDMC020_BANK_SIZE_4M 0x2 78*4882a593Smuzhiyun #define FTSDMC020_BANK_SIZE_8M 0x3 79*4882a593Smuzhiyun #define FTSDMC020_BANK_SIZE_16M 0x4 80*4882a593Smuzhiyun #define FTSDMC020_BANK_SIZE_32M 0x5 81*4882a593Smuzhiyun #define FTSDMC020_BANK_SIZE_64M 0x6 82*4882a593Smuzhiyun #define FTSDMC020_BANK_SIZE_128M 0x7 83*4882a593Smuzhiyun #define FTSDMC020_BANK_SIZE_256M 0x8 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* 86*4882a593Smuzhiyun * Arbiter Control Register 87*4882a593Smuzhiyun */ 88*4882a593Smuzhiyun #define FTSDMC020_ACR_TOC(x) ((x) & 0x1f) 89*4882a593Smuzhiyun #define FTSDMC020_ACR_TOE (1 << 8) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #endif /* __FTSDMC020_H */ 92