1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2011 Andes Technology Corporation 3*4882a593Smuzhiyun * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* FTAHBC020S - AHB Controller (Arbiter/Decoder) definitions */ 9*4882a593Smuzhiyun #ifndef __FTAHBC020S_H 10*4882a593Smuzhiyun #define __FTAHBC202S_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* Registers Offsets */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * AHB Slave BSR, offset: n * 4, n=0~31 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 18*4882a593Smuzhiyun struct ftahbc02s { 19*4882a593Smuzhiyun unsigned int s_bsr[32]; /* 0x00-0x7c - Slave n Base/Size Reg */ 20*4882a593Smuzhiyun unsigned int pcr; /* 0x80 - Priority Ctrl Reg */ 21*4882a593Smuzhiyun unsigned int tcrg; /* 0x84 - Transfer Ctrl Reg */ 22*4882a593Smuzhiyun unsigned int cr; /* 0x88 - Ctrl Reg */ 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * FTAHBC020S_SLAVE_BSR - Slave n Base / Size Register 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun #define FTAHBC020S_SLAVE_BSR_BASE(x) (((x) & 0xfff) << 20) 30*4882a593Smuzhiyun #define FTAHBC020S_SLAVE_BSR_SIZE(x) (((x) & 0xf) << 16) 31*4882a593Smuzhiyun /* The value of b(16:19)SLAVE_BSR_SIZE: 1M-2048M, must be power of 2 */ 32*4882a593Smuzhiyun #define FTAHBC020S_BSR_SIZE(x) (ffs(x) - 1) /* size of Addr Space */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* 35*4882a593Smuzhiyun * FTAHBC020S_PCR - Priority Control Register 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun #define FTAHBC020S_PCR_PLEVEL_(x) (1 << (x)) /* x: 1-15 */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* 40*4882a593Smuzhiyun * FTAHBC020S_CR - Interrupt Control Register 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun #define FTAHBC020S_CR_INTSTS (1 << 24) 43*4882a593Smuzhiyun #define FTAHBC020S_CR_RESP(x) (((x) & 0x3) << 20) 44*4882a593Smuzhiyun #define FTAHBC020S_CR_INTSMASK (1 << 16) 45*4882a593Smuzhiyun #define FTAHBC020S_CR_REMAP (1 << 0) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #endif /* __FTAHBC020S_H */ 48