1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * exynos_lcd.h - Exynos LCD Controller structures 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2001 5*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _EXYNOS_LCD_H_ 11*4882a593Smuzhiyun #define _EXYNOS_LCD_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun enum { 14*4882a593Smuzhiyun FIMD_RGB_INTERFACE = 1, 15*4882a593Smuzhiyun FIMD_CPU_INTERFACE = 2, 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun enum exynos_fb_rgb_mode_t { 19*4882a593Smuzhiyun MODE_RGB_P = 0, 20*4882a593Smuzhiyun MODE_BGR_P = 1, 21*4882a593Smuzhiyun MODE_RGB_S = 2, 22*4882a593Smuzhiyun MODE_BGR_S = 3, 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun typedef struct vidinfo { 26*4882a593Smuzhiyun ushort vl_col; /* Number of columns (i.e. 640) */ 27*4882a593Smuzhiyun ushort vl_row; /* Number of rows (i.e. 480) */ 28*4882a593Smuzhiyun ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */ 29*4882a593Smuzhiyun ushort vl_width; /* Width of display area in millimeters */ 30*4882a593Smuzhiyun ushort vl_height; /* Height of display area in millimeters */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* LCD configuration register */ 33*4882a593Smuzhiyun u_char vl_freq; /* Frequency */ 34*4882a593Smuzhiyun u_char vl_clkp; /* Clock polarity */ 35*4882a593Smuzhiyun u_char vl_oep; /* Output Enable polarity */ 36*4882a593Smuzhiyun u_char vl_hsp; /* Horizontal Sync polarity */ 37*4882a593Smuzhiyun u_char vl_vsp; /* Vertical Sync polarity */ 38*4882a593Smuzhiyun u_char vl_dp; /* Data polarity */ 39*4882a593Smuzhiyun u_char vl_bpix; /* Bits per pixel */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Horizontal control register. Timing from data sheet */ 42*4882a593Smuzhiyun u_char vl_hspw; /* Horz sync pulse width */ 43*4882a593Smuzhiyun u_char vl_hfpd; /* Wait before of line */ 44*4882a593Smuzhiyun u_char vl_hbpd; /* Wait end of line */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Vertical control register. */ 47*4882a593Smuzhiyun u_char vl_vspw; /* Vertical sync pulse width */ 48*4882a593Smuzhiyun u_char vl_vfpd; /* Wait before of frame */ 49*4882a593Smuzhiyun u_char vl_vbpd; /* Wait end of frame */ 50*4882a593Smuzhiyun u_char vl_cmd_allow_len; /* Wait end of frame */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun unsigned int win_id; 53*4882a593Smuzhiyun unsigned int init_delay; 54*4882a593Smuzhiyun unsigned int power_on_delay; 55*4882a593Smuzhiyun unsigned int reset_delay; 56*4882a593Smuzhiyun unsigned int interface_mode; 57*4882a593Smuzhiyun unsigned int mipi_enabled; 58*4882a593Smuzhiyun unsigned int dp_enabled; 59*4882a593Smuzhiyun unsigned int cs_setup; 60*4882a593Smuzhiyun unsigned int wr_setup; 61*4882a593Smuzhiyun unsigned int wr_act; 62*4882a593Smuzhiyun unsigned int wr_hold; 63*4882a593Smuzhiyun unsigned int logo_on; 64*4882a593Smuzhiyun unsigned int logo_width; 65*4882a593Smuzhiyun unsigned int logo_height; 66*4882a593Smuzhiyun int logo_x_offset; 67*4882a593Smuzhiyun int logo_y_offset; 68*4882a593Smuzhiyun unsigned long logo_addr; 69*4882a593Smuzhiyun unsigned int rgb_mode; 70*4882a593Smuzhiyun unsigned int resolution; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* parent clock name(MPLL, EPLL or VPLL) */ 73*4882a593Smuzhiyun unsigned int pclk_name; 74*4882a593Smuzhiyun /* ratio value for source clock from parent clock. */ 75*4882a593Smuzhiyun unsigned int sclk_div; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun unsigned int dual_lcd_enabled; 78*4882a593Smuzhiyun struct exynos_fb *reg; 79*4882a593Smuzhiyun struct exynos_platform_mipi_dsim *dsim_platform_data_dt; 80*4882a593Smuzhiyun } vidinfo_t; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #endif 83