1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This software is licensed under the terms of the GNU General Public 5*4882a593Smuzhiyun * License version 2, as published by the Free Software Foundation, and 6*4882a593Smuzhiyun * may be copied, distributed, and modified under those terms. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, 9*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 10*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11*4882a593Smuzhiyun * GNU General Public License for more details. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H 15*4882a593Smuzhiyun #define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* MPUMODRST */ 18*4882a593Smuzhiyun #define CPU0_RESET 0 19*4882a593Smuzhiyun #define CPU1_RESET 1 20*4882a593Smuzhiyun #define WDS_RESET 2 21*4882a593Smuzhiyun #define SCUPER_RESET 3 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* PER0MODRST */ 24*4882a593Smuzhiyun #define EMAC0_RESET 32 25*4882a593Smuzhiyun #define EMAC1_RESET 33 26*4882a593Smuzhiyun #define EMAC2_RESET 34 27*4882a593Smuzhiyun #define USB0_RESET 35 28*4882a593Smuzhiyun #define USB1_RESET 36 29*4882a593Smuzhiyun #define NAND_RESET 37 30*4882a593Smuzhiyun #define QSPI_RESET 38 31*4882a593Smuzhiyun #define SDMMC_RESET 39 32*4882a593Smuzhiyun #define EMAC0_OCP_RESET 40 33*4882a593Smuzhiyun #define EMAC1_OCP_RESET 41 34*4882a593Smuzhiyun #define EMAC2_OCP_RESET 42 35*4882a593Smuzhiyun #define USB0_OCP_RESET 43 36*4882a593Smuzhiyun #define USB1_OCP_RESET 44 37*4882a593Smuzhiyun #define NAND_OCP_RESET 45 38*4882a593Smuzhiyun #define QSPI_OCP_RESET 46 39*4882a593Smuzhiyun #define SDMMC_OCP_RESET 47 40*4882a593Smuzhiyun #define DMA_RESET 48 41*4882a593Smuzhiyun #define SPIM0_RESET 49 42*4882a593Smuzhiyun #define SPIM1_RESET 50 43*4882a593Smuzhiyun #define SPIS0_RESET 51 44*4882a593Smuzhiyun #define SPIS1_RESET 52 45*4882a593Smuzhiyun #define DMA_OCP_RESET 53 46*4882a593Smuzhiyun #define EMAC_PTP_RESET 54 47*4882a593Smuzhiyun /* 55 is empty*/ 48*4882a593Smuzhiyun #define DMAIF0_RESET 56 49*4882a593Smuzhiyun #define DMAIF1_RESET 57 50*4882a593Smuzhiyun #define DMAIF2_RESET 58 51*4882a593Smuzhiyun #define DMAIF3_RESET 59 52*4882a593Smuzhiyun #define DMAIF4_RESET 60 53*4882a593Smuzhiyun #define DMAIF5_RESET 61 54*4882a593Smuzhiyun #define DMAIF6_RESET 62 55*4882a593Smuzhiyun #define DMAIF7_RESET 63 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* PER1MODRST */ 58*4882a593Smuzhiyun #define L4WD0_RESET 64 59*4882a593Smuzhiyun #define L4WD1_RESET 65 60*4882a593Smuzhiyun #define L4SYSTIMER0_RESET 66 61*4882a593Smuzhiyun #define L4SYSTIMER1_RESET 67 62*4882a593Smuzhiyun #define SPTIMER0_RESET 68 63*4882a593Smuzhiyun #define SPTIMER1_RESET 69 64*4882a593Smuzhiyun /* 70-71 is reserved */ 65*4882a593Smuzhiyun #define I2C0_RESET 72 66*4882a593Smuzhiyun #define I2C1_RESET 73 67*4882a593Smuzhiyun #define I2C2_RESET 74 68*4882a593Smuzhiyun #define I2C3_RESET 75 69*4882a593Smuzhiyun #define I2C4_RESET 76 70*4882a593Smuzhiyun /* 77-79 is reserved */ 71*4882a593Smuzhiyun #define UART0_RESET 80 72*4882a593Smuzhiyun #define UART1_RESET 81 73*4882a593Smuzhiyun /* 82-87 is reserved */ 74*4882a593Smuzhiyun #define GPIO0_RESET 88 75*4882a593Smuzhiyun #define GPIO1_RESET 89 76*4882a593Smuzhiyun #define GPIO2_RESET 90 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* BRGMODRST */ 79*4882a593Smuzhiyun #define HPS2FPGA_RESET 96 80*4882a593Smuzhiyun #define LWHPS2FPGA_RESET 97 81*4882a593Smuzhiyun #define FPGA2HPS_RESET 98 82*4882a593Smuzhiyun #define F2SSDRAM0_RESET 99 83*4882a593Smuzhiyun #define F2SSDRAM1_RESET 100 84*4882a593Smuzhiyun #define F2SSDRAM2_RESET 101 85*4882a593Smuzhiyun #define DDRSCH_RESET 102 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* SYSMODRST*/ 88*4882a593Smuzhiyun #define ROM_RESET 128 89*4882a593Smuzhiyun #define OCRAM_RESET 129 90*4882a593Smuzhiyun /* 130 is reserved */ 91*4882a593Smuzhiyun #define FPGAMGR_RESET 131 92*4882a593Smuzhiyun #define S2F_RESET 132 93*4882a593Smuzhiyun #define SYSDBG_RESET 133 94*4882a593Smuzhiyun #define OCRAM_OCP_RESET 134 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* COLDMODRST */ 97*4882a593Smuzhiyun #define CLKMGRCOLD_RESET 160 98*4882a593Smuzhiyun /* 161-162 is reserved */ 99*4882a593Smuzhiyun #define S2FCOLD_RESET 163 100*4882a593Smuzhiyun #define TIMESTAMPCOLD_RESET 164 101*4882a593Smuzhiyun #define TAPCOLD_RESET 165 102*4882a593Smuzhiyun #define HMCCOLD_RESET 166 103*4882a593Smuzhiyun #define IOMGRCOLD_RESET 167 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* NRSTMODRST */ 106*4882a593Smuzhiyun #define NRSTPINOE_RESET 192 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* DBGMODRST */ 109*4882a593Smuzhiyun #define DBG_RESET 224 110*4882a593Smuzhiyun #endif 111